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Hitachi 16-Bit Single-Chip Microcomputer
H8S/2319, H8S/2318 Series, H8S/2319 F-ZTATTM, H8S/2318 F-ZTATTM, H8S/2315 F-ZTATTM
H8S/2319 H8S/2318 H8S/2317 H8S/2316 H8S/2315 H8S/2313 H8S/2312 H8S/2311 H8S/2310 HD64F2319 HD6432318, HD64F2318 HD6432317 HD6432316 HD64F2315 HD6432313 HD6412312 HD6432311 HD6412310
Reference Manual
-- Individual Product Specifications --
ADE-602-188A Rev. 2.0 8/24/00 Hitachi, Ltd.
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Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Main Revisions and Additions in this Edition
Page All Item Whole sections Revisions (See Manual for Details) Amendment due to the addition of the H8S/2319 F-ZTAT, H8S/2315 F-ZTAT, H8S/2316, and H8S/2313 to the product lineup. Table 1.1 Overview The product lineup added. Figure 1.1 Block Diagram Note 1 amended due to the addition of WDTOVF (FWE, EMLE). Figure 1.2 Pin Arrangement Note amended due to the addition of WDTOVF (FWE, EMLE). Figure 1.3 Pin Arrangement Note amended due to the addition of WDTOVF (FWE, EMLE). 1.4 Pin Functions in Each Operating Mode Table 1.2 Pin Functions in Each Operating Mode Functions for pins 32 to 39, 41 to 48, and 50 to 52 (TFP-100B) in flash memory programmer mode amended. Function for pin 60 (TFP-100B) amended Note 3 amended. 1.5 Pin Functions Table 1.3 Pin Functions EMLE pin added. Note 4 added. 1.6 Product Lineup 2.5 Memory Map in Each Operating Mode Note 2 added. Figure 2.1 H8S/2319 F-ZTAT Memory Map in Each Operating Mode added. Figures 2.2, 2.3, and 2.7 Memory Map in Each Operating Mode Note on reserved area added. Figure 2.4 H8S/2316 Memory Map in Each Operating Mode added. Figure 2.5 H8S/2315 F-ZTAT Memory Map in Each Operating Mode added. Figure 2.6 H8S/2313 Memory Map in Each Operating Mode added. 2.6 H8S/2318 Series Operating Modes (F-ZTAT Version) Deleted (see the hardware manual).
5 6
1.1 Overview 1.2 Block Diagram
7
1.3 Pin Arrangement
8
10
12 15 19 20 32 33 to 36, 42 37 38 to 40 41 --
Page 51
Item 3.3.3 Interrupt Exception Vector Table
Revisions (See Manual for Details) Table 3.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities Names for SCI interrupts RXI0 and RXI1 amended. Table 3.8 Interrupt Response Times Number of wait states until execution instruction ends amended. Description of bit 5 H8S/2319, H8S/2316, H8S/2315, and H8S/2313 added Table 5.23 I/O Port States in Each Processing State LWROD and DAOEn added to Legend. Figure 5.35(a) Port G Block Diagram (Pin PG0) Amended. Amended due to the addition of the H8S/2319 FZTAT to the product lineup. Table 7.8 A/D Conversion Characteristics Nonlinearity error, offset error, full-scale error, quantization error, and absolute accuracy amended. Added.
54
3.5 Interrupt Response Times
73
4.2.5 Bus Control Register L (BCRL) 5.13 Pin States
177
200 225 252
5.14.11 Port G 6.11 ROM 7.1.4 A/D Conversion Characteristics
254 to 262
7.2 Electrical Characteristics of Mask ROM Version (H8S/2318, H8S/2317) in Low-Voltage Operation 7.3 Electrical Characteristics of F-ZTAT Version (H8S/2318) 7.3.2 DC Characteristics
263
Table 7.19 Absolute Maximum Ratings Conditions A and B added. Note amended. Tables 7.20 (a) and (b) DC Characteristics Maximum value of input leakage current, typical and maximum values of current dissipation, typical and maximum values of analog power supply voltage, typical and maximum values of reference power supply voltage, and equation in note 4 amended. Table 7.25 Timing of On-Chip Supporting Modules WDT overflow output delay time deleted. Table 7.26 A/D Conversion Characteristics Nonlinearity error, offset error, full-scale error, quantization error, and absolute accuracy amended.
264 to 267
--
7.3.3 AC Characteristics
275
7.3.4 A/D Conversion Characteristics
Page 277 to 280 281 to 298 --
Item 7.3.6 Flash Memory Characteristics 7.4 Electrical Characteristics of F-ZTAT Version (H8S/2315)
Revisions (See Manual for Details) Tables 7.28 (a) and (b) Flash Memory Characteristics Completely replaced. Added. 7.3.1 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions (in the 1st Edition) Deleted (see the hardware manual).
305
8.1 List of Registers (Address Order)
H'FFC8: FLMCR1 H'FFC9: FLMCR2 H'FFCB: EBR2 Amended. H'FED5: BCRL Description of bit 5 amended. H'FF37: DTVECR Description of bit 7 amended. H'FFC8: FLMCR1 Amended. H'FFC9: FLMCR2 Amended. H'FFCB: EBR2 Amended.
345 351 402, 403 404, 405 406
8.3 Functions
Organization of H8S/2319, H8S/2318 Series Reference Manual
The following manuals are available for H8S/2319, H8S/2318 Series. Table 1
Title H8S/2600 Series, H8S/2000 Series Programming Manual H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual H8S/2319, H8S/2318 Series, H8S/2319 F-ZTATTM, H8S/2318 F-ZTATTM, H8S/2315 F-ZTATTM Reference Manual
Manuals
Document Code ADE-602-083A ADE-602-171A (in preparation) ADE-602-188A
The H8S/2600 Series, H8S/2000 Series Programming Manual gives a detailed description of the architecture and instruction set of the H8S/2000 CPU. The H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual describes the operation of on-chip functions, and gives a detailed description of the related registers. The H8S/2319, H8S/2318 Series, H8S/2319 F-ZTATTM, H8S/2318 F-ZTATTM, H8S/2315 F-ZTATTM Reference Manual mainly covers information specific to H8S/2319, H8S/2318 Series and H8S/2318 F-ZTATTM products, including pin arrangement, I/O ports, MCU operating modes (address maps), interrupt vectors, bus control, and electrical characteristics, and also includes a brief description of all I/O registers for the convenience of the user. The contents of H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual and the H8S/2319, H8S/2318 Series, H8S/2319 F-ZTATTM, H8S/2318 F-ZTATTM, H8S/2315 F-ZTATTM Reference Manual are summarized in table 2.
Table 2
No. 1 Item
Contents of Hardware Manual and Reference Manual
Hardware Manual Reference Manual (including pin arrangement)
Overview
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MCU operating modes (including address maps) Exception handling Interrupt controller Bus controller DMA controller (DMAC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG) 8-bit timers Watchdog timer Serial communication interface (SCI) Smart card interface A/D converter D/A converter RAM ROM (flash memory) Clock pulse generator Power-down modes I/O ports (including port block diagrams) Electrical characteristics Register reference chart (in address order, with function summary) Instruction set Package dimension diagrams
--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
: Included : Included (with detailed register descriptions) --: Not included
The following chart shows where to find various kinds of information for different purposes.
For product evaluation information, or comparative specification information for current users of Hitachi products For product specifications Overview Pin arrangement diagram Block diagrams of function modules Pin functions Electrical characteristics 1.1 Overview 1.3 Pin Arrangement Section 6 Peripheral Block Diagrams 1.5 Pin Functions Section 7 Electrical Characteristics
For detailed information on functions
For details of operation of modules I/O port information Interrupts and exception handling Information on other modules Section 5 I/O Ports Section 3 Exception Handling and Interrupt Controller H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual 1.5 Pin Functions
Pin functions
For information on operating modes List Detailed descriptions 1.4 Pin Functions in Each Operating Mode Section 2 MCU Operating Modes
For use as design material
For information on registers List To find a register from its address To find register information by function Setting procedure and notes Section 8 registers 8.1 List of Registers (Address Order) 8.2 List of Registers (By Module) H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, H8S/2318 Series Hardware Manual
For information on instructions List Operation description and notes Program examples H8S/2600 Series, H8S/2000 Series Programming Manual
The H8S/2339 Series, H8S/2338 Series, H8S/2329 Series, H8S/2328 Series, H8S/2319 Series, and H8S/2318 Series have the on-chip modules shown below Table 3 H8S/2339, H8S/2338, H8S/2329, H8S/2328, H8S/2319, and H8S/2318 Series On-Chip Modules
H8S/2339 Series, H8S/2338 Series H8S/2329 Series, H8S/2328 Series H8S/2319 Series, H8S/2318 Series
On-Chip Module CPU Bus controller (BUSC) DRAM controller DMA controller (DMAC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Programable pulse generator (PPG) 8-bit timer Watchdog timer Serial communication interface (SCI) A/D converter D/A converter Interrupt controller (INTC) Memory*
x x
(6 channels)
(6 channels)
(6 channels)
x
(2 channels)
(2 channels)
(2 channels)
(3 channels)
(3 channels)
(2 channels)
(12 channels) (4 channels)
(8 channels) (2 channels)
(8 channels) (2 channels)
Product Code H8S/2339 H8S/2338 H8S/2337 H8S/2332
ROM RAM (kbytes) (kbytes) 384 256 128 -- 32 8 8 8
Product Code H8S/2329 H8S/2328 H8s/2327 H8S/2324 H8S/2323 H8S/2322R H8S/2320
ROM RAM (kbytes) (kbytes) 384 256 128 -- 32 -- -- 32 8 8 32 8 8 4
Product Code H8S/2319 H8S/2318 H8S/2317 H8S/2316 H8S/2315 H8S/2313 H8S/2312 H8S/2311 H8S/2310
ROM RAM (kbytes) (kbytes) 512 256 128 64 384 64 -- 32 -- 8 8 8 8 8 2 8 2 2
: On-chip x : Not on-chip
Note: * See the reference manual of each series for details.
Contents
Section 1
1.1 1.2 1.3 1.4 1.5 1.6 1.7
Overview............................................................................................................ 1 Overview ............................................................................................................................ 1 Block Diagram ................................................................................................................... 6 Pin Arrangement ................................................................................................................ 7 Pin Functions in Each Operating Mode ............................................................................. 9 Pin Functions...................................................................................................................... 13 Product Lineup ................................................................................................................... 20 Package Dimensions .......................................................................................................... 21 MCU Operating Modes................................................................................. 23
23 23 24 25 26 26 26 28 28 28 28 29 29 29 29 30 30 30 30 30 31 31 Overview ............................................................................................................................ 2.1.1 Operating Mode Selection (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions)....................................... 2.1.2 Operating Mode Selection (Mask ROM, ROMless, and H8S/2319 F-ZTAT Versions)................................. 2.1.3 Register Configuration .............................................................................................. Register Descriptions ......................................................................................................... 2.2.1 Mode Control Register (MDCR) .......................................................................... 2.2.2 System Control Register (SYSCR)....................................................................... 2.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Version Only) .......................... Operating Mode Descriptions ............................................................................................ 2.3.1 Modes 1 to 3.......................................................................................................... 2.3.2 Mode 4 (Expanded Mode with On-Chip ROM Disabled) .................................... 2.3.3 Mode 5 (Expanded Mode with On-Chip ROM Disabled) .................................... 2.3.4 Mode 6 (Expanded Mode with On-Chip ROM Enabled)..................................... 2.3.5 Mode 7 (Single-Chip Mode)................................................................................. 2.3.6 Modes 8 and 9 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only) ..... 2.3.7 Mode 10 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only)............... 2.3.8 Mode 11 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only)............... 2.3.9 Modes 12 and 13 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only). 2.3.10 Mode 14 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only)............... 2.3.11 Mode 15 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only)............... Pin Functions in Each Operating Mode ............................................................................. Memory Map in Each Operating Mode .............................................................................
Section 2
2.1
2.2
2.3
2.4 2.5
Section 3
3.1 3.2
Exception Handling and Interrupt Controller......................................... 43
Overview ............................................................................................................................ 43 3.1.1 Exception Handling Types and Priority................................................................ 43 Interrupt Controller ............................................................................................................ 44
i
3.3
3.4 3.5 3.6
3.2.1 Interrupt Controller Features................................................................................. 3.2.2 Pin Configuration .................................................................................................. Interrupt Sources ................................................................................................................ 3.3.1 External Interrupts................................................................................................. 3.3.2 Internal Interrupts.................................................................................................. 3.3.3 Interrupt Exception Vector Table ......................................................................... Interrupt Control Modes and Interrupt Operation .............................................................. Interrupt Response Times................................................................................................... DTC Activation by Interrupt .............................................................................................. 3.6.1 Overview............................................................................................................... 3.6.2 Block Diagram ...................................................................................................... 3.6.3 Operation...............................................................................................................
44 44 45 45 46 46 52 54 55 55 55 56 61 61 61 62 63 64 65 65 66 66 71 72 74 74 75 76 76 77 79 79 79 81 81 81 83 84 84 87 87 87
Section 4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
ii
Bus Controller .................................................................................................. Overview ............................................................................................................................ 4.1.1 Features ................................................................................................................. 4.1.2 Block Diagram ...................................................................................................... 4.1.3 Pin Configuration .................................................................................................. 4.1.4 Register Configuration .......................................................................................... Register Descriptions ......................................................................................................... 4.2.1 Bus Width Control Register (ABWCR) ............................................................... 4.2.2 Access State Control Register (ASTCR) .............................................................. 4.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 4.2.4 Bus Control Register H (BCRH) .......................................................................... 4.2.5 Bus Control Register L (BCRL) ........................................................................... Overview of Bus Control ................................................................................................... 4.3.1 Area Partitioning................................................................................................... 4.3.2 Bus Specifications................................................................................................. 4.3.3 Memory Interfaces ................................................................................................ 4.3.4 Advanced Mode .................................................................................................... 4.3.5 Chip Select Signals ............................................................................................... Basic Bus Interface............................................................................................................. 4.4.1 Overview............................................................................................................... 4.4.2 Wait Control.......................................................................................................... Burst ROM Interface .......................................................................................................... 4.5.1 Overview............................................................................................................... 4.5.2 Basic Timing......................................................................................................... 4.5.3 Wait Control.......................................................................................................... Idle Cycle ........................................................................................................................... 4.6.1 Operation............................................................................................................... 4.6.2 Pin States in Idle Cycle ......................................................................................... Bus Release ........................................................................................................................ 4.7.1 Overview...............................................................................................................
4.8
4.9
4.7.2 Operation............................................................................................................... 4.7.3 Pin States in External-Bus-Released State............................................................ 4.7.4 Transition Timing ................................................................................................. 4.7.5 Usage Note ............................................................................................................ Bus Arbitration................................................................................................................... 4.8.1 Overview............................................................................................................... 4.8.2 Operation............................................................................................................... 4.8.3 Bus Transfer Timing ............................................................................................. 4.8.4 Note on Use of External Bus Release ................................................................... Bus Controller Operation in a Reset ..................................................................................
87 88 89 90 90 90 90 90 91 91
Section 5
5.1 5.2
5.3
5.4
5.5
5.6
5.7
5.8
I/O Ports ............................................................................................................. 93 Overview ............................................................................................................................ 93 Port 1 .................................................................................................................................. 98 5.2.1 Overview............................................................................................................... 98 5.2.2 Register Configuration .......................................................................................... 99 5.2.3 Pin Functions......................................................................................................... 101 Port 2 .................................................................................................................................. 110 5.3.1 Overview............................................................................................................... 110 5.3.2 Register Configuration .......................................................................................... 110 5.3.3 Pin Functions......................................................................................................... 112 Port 3 .................................................................................................................................. 120 5.4.1 Overview............................................................................................................... 120 5.4.2 Register Configuration .......................................................................................... 120 5.4.3 Pin Functions......................................................................................................... 123 Port 4 .................................................................................................................................. 125 5.5.1 Overview............................................................................................................... 125 5.5.2 Register Configuration .......................................................................................... 125 5.5.3 Pin Functions......................................................................................................... 126 Port A ................................................................................................................................. 126 5.6.1 Overview............................................................................................................... 126 5.6.2 Register Configuration .......................................................................................... 127 5.6.3 Pin Functions......................................................................................................... 130 5.6.4 MOS Input Pull-Up Function................................................................................ 131 Port B ................................................................................................................................. 132 5.7.1 Overview............................................................................................................... 132 5.7.2 Register Configuration .......................................................................................... 133 5.7.3 Pin Functions......................................................................................................... 135 5.7.4 MOS Input Pull-Up Function................................................................................ 137 Port C ................................................................................................................................. 138 5.8.1 Overview............................................................................................................... 138 5.8.2 Register Configuration .......................................................................................... 139 5.8.3 Pin Functions......................................................................................................... 141
iii
5.9
5.10
5.11
5.12
5.13 5.14
5.8.4 MOS Input Pull-Up Function................................................................................ 143 Port D ................................................................................................................................. 144 5.9.1 Overview............................................................................................................... 144 5.9.2 Register Configuration .......................................................................................... 145 5.9.3 Pin Functions......................................................................................................... 147 5.9.4 MOS Input Pull-Up Function................................................................................ 148 Port E.................................................................................................................................. 150 5.10.1 Overview............................................................................................................... 150 5.10.2 Register Configuration .......................................................................................... 151 5.10.3 Pin Functions......................................................................................................... 153 5.10.4 MOS Input Pull-Up Function................................................................................ 154 Port F .................................................................................................................................. 156 5.11.1 Overview............................................................................................................... 156 5.11.2 Register Configuration .......................................................................................... 157 5.11.3 Pin Functions......................................................................................................... 162 Port G ................................................................................................................................. 165 5.12.1 Overview............................................................................................................... 165 5.12.2 Register Configuration .......................................................................................... 166 5.12.3 Pin Functions......................................................................................................... 170 Pin States ............................................................................................................................ 172 5.13.1 Port States in Each Mode ...................................................................................... 172 I/O Port Block Diagrams.................................................................................................... 178 5.14.1 Port 1..................................................................................................................... 178 5.14.2 Port 2..................................................................................................................... 182 5.14.3 Port 3..................................................................................................................... 183 5.14.4 Port 4..................................................................................................................... 186 5.14.5 Port A .................................................................................................................... 187 5.14.6 Port B .................................................................................................................... 188 5.14.7 Port C .................................................................................................................... 189 5.14.8 Port D .................................................................................................................... 190 5.14.9 Port E..................................................................................................................... 191 5.14.10 Port F..................................................................................................................... 192 5.14.11 Port G .................................................................................................................... 200
Section 6
6.1
Supporting Module Block Diagrams......................................................... 205
6.2
6.3
iv
Interrupt Controller ............................................................................................................ 205 6.1.1 Features ................................................................................................................. 205 6.1.2 Block Diagram ...................................................................................................... 205 6.1.3 Pins........................................................................................................................ 206 Data Transfer Controller .................................................................................................... 206 6.2.1 Features ................................................................................................................. 206 6.2.2 Block Diagram ...................................................................................................... 207 16-Bit Timer Pulse Unit ..................................................................................................... 208
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.3.1 Features ................................................................................................................. 208 6.3.2 Block Diagram ...................................................................................................... 209 6.3.3 Pins........................................................................................................................ 210 8-Bit Timer......................................................................................................................... 211 6.4.1 Features ................................................................................................................. 211 6.4.2 Block Diagram ...................................................................................................... 212 6.4.3 Pins........................................................................................................................ 213 Watchdog Timer................................................................................................................. 214 6.5.1 Features ................................................................................................................. 214 6.5.2 Block Diagram ...................................................................................................... 214 6.5.3 Pins........................................................................................................................ 215 Serial Communication Interface......................................................................................... 215 6.6.1 Features ................................................................................................................. 215 6.6.2 Block Diagram ...................................................................................................... 216 6.6.3 Pins........................................................................................................................ 217 Smart Card Interface .......................................................................................................... 218 6.7.1 Features ................................................................................................................. 218 6.7.2 Block Diagram ...................................................................................................... 218 6.7.3 Pins........................................................................................................................ 219 A/D Converter (8 Analog Input Channel Version) ............................................................ 219 6.8.1 Features ................................................................................................................. 219 6.8.2 Block Diagram ...................................................................................................... 220 6.8.3 Pins........................................................................................................................ 221 D/A Converter .................................................................................................................... 222 6.9.1 Features ................................................................................................................. 222 6.9.2 Block Diagram ...................................................................................................... 222 6.9.3 Pins........................................................................................................................ 223 RAM................................................................................................................................... 224 6.10.1 Features ................................................................................................................. 224 6.10.2 Block Diagram ...................................................................................................... 224 ROM (H8S/2319)............................................................................................................... 225 6.11.1 Features ................................................................................................................. 225 6.11.2 Block Diagrams..................................................................................................... 225 ROM................................................................................................................................... 227 6.12.1 Features ................................................................................................................. 227 6.12.2 Block Diagrams..................................................................................................... 227 Clock Pulse Generator ....................................................................................................... 229 6.13.1 Features ................................................................................................................. 229 6.13.2 Block Diagram ...................................................................................................... 229
Section 7
7.1
Electrical Characteristics............................................................................... 231 Electrical Characteristics of Mask ROM Version (H8S/2318, H8S/2317, H8S/2316, H8S/2313, H8S/2311) and ROMless Version (H8S/2312, H8S/2310) ............................. 231
v
7.2
7.3
7.4
7.5
7.1.1 Absolute Maximum Ratings ................................................................................. 231 7.1.2 DC Characteristics ................................................................................................ 232 7.1.3 AC Characteristics ................................................................................................ 234 7.1.4 A/D Conversion Characteristics ........................................................................... 252 7.1.5 D/A Conversion Characteristics ........................................................................... 253 Electrical Characteristics of Mask ROM Version (H8S/2318, H8S/2317) in Low-Voltage Operation ................................................................................................. 254 7.2.1 Absolute Maximum Ratings ................................................................................. 254 7.2.2 DC Characteristics ................................................................................................ 255 7.2.3 AC Characteristics ................................................................................................ 257 7.2.4 A/D Conversion Characteristics ........................................................................... 262 7.2.5 D/A Conversion Characteristics ........................................................................... 262 Electrical Characteristics of F-ZTAT Version (H8S/2318) ............................................... 263 7.3.1 Absolute Maximum Ratings ................................................................................. 263 7.3.2 DC Characteristics ................................................................................................ 264 7.3.3 AC Characteristics ................................................................................................ 269 7.3.4 A/D Conversion Characteristics ........................................................................... 275 7.3.5 D/A Conversion Characteristics ........................................................................... 276 7.3.6 Flash Memory Characteristics .............................................................................. 277 Electrical Characteristics of F-ZTAT Version (H8S/2315) (Under Development)........... 281 7.4.1 Absolute Maximum Ratings ................................................................................. 281 7.4.2 DC Characteristics ................................................................................................ 282 7.4.3 AC Characteristics ................................................................................................ 287 7.4.4 A/D Conversion Characteristics ........................................................................... 293 7.4.5 D/A Conversion Characteristics ........................................................................... 294 7.4.6 Flash Memory Characteristics .............................................................................. 295 Usage Note ......................................................................................................................... 298
Section 8
8.1 8.2 8.3
Registers............................................................................................................. 299 List of Registers (Address Order) ...................................................................................... 299 List of Registers (By Module) ........................................................................................... 307 Functions ............................................................................................................................ 315
vi
Section 1 Overview
1.1 Overview
The H8S/2319 and H8S/2318 Series are series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include data transfer controller (DTC) bus master, ROM and RAM memory, a 16-bit timer pulse unit (TPU), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports. Single-power-supply flash memory (F-ZTATTM*) and mask ROM versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. ROM is connected to the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The features of the H8S/2319 and H8S/2318 Series are shown in table 1.1. Note: * F-ZTAT is a trademark of Hitachi, Ltd.
1
Table 1.1
Item CPU
Overview
Specification * General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for realtime control Maximum clock rate: 25 MHz High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 40 ns (at 25 MHz operation) 16 x 16-bit register-register multiply: 800 ns (at 25 MHz operation) 32 / 16-bit register-register divide: 800 ns (at 25 MHz operation) Instruction set suitable for high-speed operation Sixty-five basic instructions 8/16/32-bit data transfer, arithmetic, and logic instructions Unsigned/signed multiply and divide instructions Powerful bit-manipulation instructions CPU operating mode Advanced mode: 16-Mbyte address space Address space divided into 8 areas, with bus specifications settable independently for each area Chip select output possible for each area Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable External bus release function Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC
*
*
* Bus controller * * * * * * * Data transfer controller (DTC) * * * *
2
Item 16-bit timer pulse unit (TPU) 8-bit timer, 2 channels Watchdog timer Serial communication interface (SCI), 2 channels A/D converter
Specification * * * * * * * * * * * * * * * * * * * * * 6-channel 16-bit timer on-chip Pulse I/O processing capability for up to 16 pins Automatic 2-phase encoder count capability 8-bit up-counter (external event count capability) Two time constant registers Two-channel connection possible Watchdog timer or interval timer selectable Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: 10 bits Input: 8 channels 6.7 s minimum conversion time (at 20 MHz operation) Single or scan mode selectable Sample-and-hold function A/D conversion can be activated by external trigger or timer trigger Resolution: 8 bits Output: 2 channels 71 input/output pins, 8 input-only pins Flash memory and mask ROM High-speed static RAM ROM 512 kbytes 256 kbytes 128 kbytes 64 kbytes 384 kbytes 64 kbytes -- 32 kbytes -- RAM 8 kbytes 8 kbytes 8 kbytes 8 kbytes 8 kbytes 2 kbytes 8 kbytes 2 kbytes 2 kbytes
D/A converter I/O ports Memory
Product Name H8S/2319* H8S/2318 H8S/2317 H8S/2316 H8S/2315* H8S/2313 H8S/2312 H8S/2311 H8S/2310 Note: * Under development Interrupt controller * * *
Nine external interrupt pins (NMI, IRQ0 to IRQ7) 43 internal interrupt sources Eight priority levels settable
3
Item Power-down state
Specification * * * * * * * Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Variable clock division ratio Eight MCU operating modes (H8S/2318 F-ZTAT, H8S/2315 F-ZTAT) External Data Bus On-Chip Initial ROM Value -- -- Maximum Value --
Operating modes
CPU Operating Mode Mode Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Advanced User program mode -- -- Advanced Boot mode -- Advanced Expanded mode with on-chip ROM disabled Expanded mode with on-chip ROM enabled Single-chip mode -- -- --
Disabled 16 bits 8 bits Enabled 8 bits -- -- --
16 bits 16 bits 16 bits -- --
Enabled
8 bits --
16 bits -- --
--
--
Enabled
8 bits --
16 bits --
4
Item Operating modes
Specification * Four MCU operating modes (mask ROM version and ROMless version H8S/2319 F-ZTAT) CPU Operating Mode -- External Data Bus Description -- On-Chip ROM -- Initial Value -- Maximum Value --
Mode 1 2 3 4* 5* 6 7 Clock pulse * generator Package Product lineup * *
Advanced
Expanded mode with onchip ROM disabled Expanded mode with onchip ROM disabled Expanded mode with onchip ROM enabled Single-chip mode
Disabled Disabled Enabled Enabled
16 bits 8 bits 8 bits --
16 bits 16 bits 16 bits --
Note: * Only modes 4 and 5 are provided in the ROMless version. Built-in duty correction circuit 100-pin plastic TQFP (TFP-100B) 100-pin plastic QFP (FP-100A) Condition A Operating power supply voltage Operating frequency Model HD64F2319 HD64F2318 HD6432318 HD6432317 HD6432316 HD64F2315 HD6432313 HD6412312 HD6432311 HD6412310 O: Products in the current lineup Notes: 1. Ta = -40C to 85C (wide-range specifications) is not available for condition C. 2. Under development 3. In planning stage 5 2.7 to 3.6 V 2 to 20 MHz * *
3 3
Condition B 3.0 to 3.6 V 2 to 25 MHz *
2
Condition C* 1 2.4 to 3.6 V 2 to 14 MHz -- -- O O *2 -- *2 -- -- --
O O O O *2 O O O O
O O O *3 O O O O
1.2
Block Diagram
PD7/ D15 PD6/ D14 PD5/ D13 PD4/ D12 PD3/ D11 PD2/ D10 PD1/ D9 PD0/ D8 PE7/ D7 PE6/ D6 PE5/ D5 PE4/ D4 PE3/ D3 PE2/ D2 PE1/ D1 PE0/ D0 Port E
VCC VCC VCC VSS VSS VSS VSS VSS VSS
Port D
H8S/2000 CPU
Internal address bus
Internal data bus
Bus controller
MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF (FWE, EMLE)*1 NMI
Clock pulse generator
Port A
PA3/A19 PA2/A18 PA1/A17 PA0/A16
Interrupt controller PF7/ o PF6/ AS PF5/ RD PF4/ HWR PF3/ LWR/ IRQ3 PF2/ WAIT/IRQ2/ DREQO PF1/ BACK/ IRQ1/CS5 PF0/ BREQ/IRQ0/ CS4 PG4/ CS0 PG3/ CS1/CS7 PG2/ CS2 PG1/ CS3/IRQ7/CS6 PG0/ ADTRG/ IRQ6 DTC ROM*2
Port F
Peripheral address bus
Port B
Peripheral data bus
PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/ A11 PB2/A10 PB1/A9 PB0/A8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P35/SCK1/IRQ5 P34/SCK0/IRQ4 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0
Port C
RAM
Port G
WDT
8-bit timer
Port 3
SCI TPU
D/A converter
A/D converter
Port 1
Port 2 Vref AVCC AVSS
Port 4 P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1 P15/TIOCB1/TCLKC P16/TIOCA2 P17/TIOCB2/TCLKD
Notes: 1. The FWE pin function is only available on the H8S/2318 F-ZTAT and H8S/2315 F-ZTAT versions. The EMLE pin function is only available on the H8S/2319 F-ZTAT version. The WDTOVF pin function is not available on the F-ZTAT versions. 2. ROM is not supported on the ROMless version.
Figure 1.1 Block Diagram
6
P20/TIOCA3 P21/TIOCB3 P22/TIOCC3/TMRI0 P23/TIOCD3/TMCI0 P24/TIOCA4/TMRI1 P25/TIOCB4/TMCI1 P26/TIOCA5/TMO0 P27/TIOCB5/TMO1
1.3
Pin Arrangement
PF2/WAIT/IRQ2/BREQO WDTOVF (FWE, EMLE)*
PF1/BACK/IRQ1/CS5
P23/TIOCD3/TMCI0
PF3/LWR/IRQ3
P22/TIOCC3/TMRI0
P21/TIOCB3
PF4/HWR
P20/TIOCA3
PA3/A19 53
PA2/A18 52
PF5/RD
PF6/AS
PF7/o
75
74
73
72
71
70
69
68
VSS
67
66
65
64
63
62
61
60
59
58
57
56
55
54
PF0/BREQ/IRQ0/CS4 AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P24/TIOCA4/TMRI1 P25/TIOCB4/TMCI1 P26/TIOCA5/TMO0 P27/TIOCB5/TMO1 PG0/ADTRG/IRQ6 PG1/CS3/IRQ7/CS6 PG2/CS2 PG3/CS1/CS7 PG4/CS0 VCC P10/TIOCA0/A20 P11/TIOCB0/A21
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
PA1/A17
EXTAL
STBY
XTAL
MD2
MD1
MD0
RES
VCC
NMI
PA0/A16 VSS PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 VCC PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 VSS PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11
P12/TIOCC0/TCLKA/A22
P13/TIOCD0/TCLKB/A23
P15/TIOCB1/TCLKC
P17/TIOCB2/TCLKD
P34/SCK0/IRQ4
P35/SCK1/IRQ5
P14/TIOCA1
P16/TIOCA2
P30/TxD0
P31/TxD1
P32/RxD0
P33/RxD1
Note: * The FWE pin function is only available on the H8S/2318 F-ZTAT and H8S/2315 F-ZTAT versions. The EMLE pin function is only available on the H8S/2319 F-ZTAT version. The WDTOVF pin function is not available on the F-ZTAT versions.
Figure 1.2 Pin Arrangement (TFP-100B: Top View)
PD2/D10
PD0/D8
PD1/D9
PE4/D4
PE5/D5
PE6/D6
PE0/D0
PE1/D1
PE2/D2
PE3/D3
PE7/D7
VSS
VSS
7
Note: * The FWE pin function is only available on the H8S/2318 F-ZTAT and H8S/2315 F-ZTAT versions. The EMLE pin function is only available on the H8S/2319 F-ZTAT version. The WDTOVF pin function is not available on the F-ZTAT versions.
8
P10/TIOCA0/A20 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22 P13/TIOCD0/TCLKB/A23 P14/TIOCA1 P15/TIOCB1/TCLKC P16/TIOCA2 P17/TIOCB2/TCLKD VSS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 VSS PE4/D4 PE5/D5 PE6/D6 PE7/D7 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS VSS P24/TIOCA4/TMRI1 P25/TIOCB4/TMCI1 P26/TIOCA5/TMO0 P27/TIOCB5/TMO1 PG0/ADTRG/IRQ6 PG1/CS3/IRQ7/CS6 PG2/CS2 PG3/CS1/CS7 PG4/CS0 VCC
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
Vref AVCC PF0/BREQ/IRQ0/CS4 PF1/BACK/IRQ1/CS5 PF2/WAIT/IRQ2/BREQO PF3/LWR/IRQ3 PF4/HWR PF5/RD PF6/AS PF7/o VSS EXTAL XTAL VCC STBY NMI RES MD2 WDTOVF (FWE, EMLE)* P23/TIOCD3/TMCI0 MD1 MD0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 PA3/A19 PA2/A18 PA1/A17 PA0/A16 VSS
PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 VCC PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 VSS PD7/D15 PD6/D14
Figure 1.3 Pin Arrangement (FP-100A: Top View)
1.4
Pin Functions in Each Operating Mode
Table 1.2 shows the pin functions in each of the operating modes. Table 1.2
Pin No. TFP-100B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 FP-100A 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Mode 4 P12/TIOCC0/ TCLKA/A22 P13/TIOCD0/ TCLKB/A23 P14/TIOCA1 P15/TIOCB1/ TCLKC P16/TIOCA2 P17/TIOCB2/ TCLKD V SS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 V SS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 Mode 5 P12/TIOCC0/ TCLKA/A22 P13/TIOCD0/ TCLKB/A23 P14/TIOCA1 P15/TIOCB1/ TCLKC P16/TIOCA2 P17/TIOCB2/ TCLKD V SS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 V SS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10 Mode 6* 1 P12/TIOCC0/ TCLKA/A22 P13/TIOCD0/ TCLKB/A23 P14/TIOCA1 P15/TIOCB1/ TCLKC P16/TIOCA2 P17/TIOCB2/ TCLKD V SS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 PE0/D0 PE1/D1 PE2/D2 PE3/D3 V SS PE4/D4 PE5/D5 PE6/D6 PE7/D7 D8 D9 D10
Pin Functions in Each Operating Mode
Pin Name Mode 7* 1 P12/TIOCC0/ TCLKA P13/TIOCD0/ TCLKB P14/TIOCA1 P15/TIOCB1/ TCLKC P16/TIOCA2 P17/TIOCB2/ TCLKD V SS P30/TxD0 P31/TxD1 P32/RxD0 P33/RxD1 P34/SCK0/IRQ4 P35/SCK1/IRQ5 PE0 PE1 PE2 PE3 V SS PE4 PE5 PE6 PE7 PD0 PD1 PD2 Flash Memory Programmer Mode* 2 NC NC NC NC NC NC V SS NC NC NC NC NC NC NC NC NC NC V SS NC NC NC NC FO0 FO1 FO2
9
Pin No. TFP-100B 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 FP-100A 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Mode 4 D11 D12 D13 D14 D15 V SS A0 A1 A2 A3 A4 A5 A6 A7 V CC A8 A9 A10 A11 A12 A13 A14 A15 V SS A16 A17 A18 A19 P20/TIOCA3 P21/TIOCB3 P22/TIOCC3/ TMRI0 MD0 MD1 P23/TIOCD3/ TMCI0 WDTOVF (FWE, EMLE)* 3 Mode 5 D11 D12 D13 D14 D15 V SS A0 A1 A2 A3 A4 A5 A6 A7 V CC A8 A9 A10 A11 A12 A13 A14 A15 V SS A16 A17 A18 A19 P20/TIOCA3 P21/TIOCB3 P22/TIOCC3/ TMRI0 MD0 MD1 P23/TIOCD3/ TMCI0 WDTOVF (FWE, EMLE)* 3 Mode 6* 1 D11 D12 D13 D14 D15 V SS
Pin Name Mode 7* 1 PD3 PD4 PD5 PD6 PD7 V SS PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 V CC PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 V SS PA0 PA1 PA2 PA3 P20/TIOCA3 P21/TIOCB3 P22/TIOCC3/ TMRI0 MD0 MD1 P23/TIOCD3/ TMCI0 WDTOVF (FWE, EMLE)* 3 Flash Memory Programmer Mode* 2 FO3 FO4 FO5 FO6 FO7 V SS A0 A1 A2 A3 A4 A5 A6 A7 V CC A8 A9 A10 A11 A12 A13 A14 A15 V SS A16 A17 A18 NC OE CE WE V SS V SS V CC FWE
PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 V CC PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 V SS PA0/A16 PA1/A17 PA2/A18 PA3/A19 P20/TIOCA3 P21/TIOCB3 P22/TIOCC3/ TMRI0 MD0 MD1 P23/TIOCD3/ TMCI0 WDTOVF (FWE, EMLE)* 3
10
Pin No. TFP-100B 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 FP-100A 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Mode 4 MD2 RES NMI STBY V CC XTAL EXTAL V SS PF7/o PF6/AS RD HWR PF3/LWR/IRQ3 PF2/WAIT/ IRQ2/DREQO PF1/BACK/ IRQ1/CS5 PF0/BREQ/ IRQ0/CS4 AVCC V ref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS V SS P24/TIOCA4/ TMRI1 P25/TIOCB4/ TMCI1 Mode 5 MD2 RES NMI STBY V CC XTAL EXTAL V SS PF7/o PF6/AS RD HWR PF3/LWR/IRQ3 PF2/WAIT/ IRQ2/DREQO PF1/BACK/ IRQ1/CS5 PF0/BREQ/ IRQ0/CS4 AVCC V ref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS V SS P24/TIOCA4/ TMRI1 P25/TIOCB4/ TMCI1 Mode 6* 1 MD2 RES NMI STBY V CC XTAL
Pin Name Mode 7* 1 MD2 RES NMI STBY V CC XTAL EXTAL V SS PF7/o PF6 PF5 PF4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/IRQ0 AVCC V ref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS V SS P24/TIOCA4/ TMRI1 P25/TIOCB4/ TMCI1 Flash Memory Programmer Mode* 2 V SS RES V CC V CC V CC XTAL EXTAL V SS NC NC NC NC NC V CC V SS V SS V CC V CC NC NC NC NC NC NC NC NC V SS V SS NC V SS
EXTAL V SS PF7/o PF6/AS RD HWR PF3/LWR/IRQ3 PF2/WAIT/ IRQ2/DREQO PF1/BACK/ IRQ1/CS5 PF0/BREQ/ IRQ0/CS4 AVCC V ref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 AVSS V SS P24/TIOCA4/ TMRI1 P25/TIOCB4/ TMCI1
11
Pin No. TFP-100B 91 92 93 94 95 96 97 98 99 100 FP-100A 93 94 95 96 97 98 99 100 1 2 Mode 4 P26/TIOCA5/ TMO0 P27/TIOCB5/ TMO1 PG0/IRQ6/ ADTRG PG1/CS3/ IRQ7/CS6 PG2/CS2 PG3/CS1/CS7 PG4/CS0 V CC P10/TIOCA0/A20 P11/TIOCB0/A21 Mode 5 P26/TIOCA5/ TMO0 P27/TIOCB5/ TMO1 PG0/IRQ6/ ADTRG PG1/CS3/ IRQ7/CS6 PG2/CS2 PG3/CS1/CS7 PG4/CS0 V CC P10/TIOCA0/A20 P11/TIOCB0/A21 Mode 6* 1
Pin Name Mode 7* 1 P26/TIOCA5/ TMO0 P27/TIOCB5/ TMO1 PG0/IRQ6/ ADTRG PG1/IRQ7 PG2 PG3 PG4 V CC P10/TIOCA0 P11/TIOCB0 Flash Memory Programmer Mode* 2 NC NC NC NC NC NC NC V CC NC NC
P26/TIOCA5/ TMO0 P27/TIOCB5/ TMO1 PG0/IRQ6/ ADTRG PG1/CS3/ IRQ7/CS6 PG2/CS2 PG3/CS1/CS7 PG4/CS0 V CC P10/TIOCA0/A20 P11/TIOCB0/A21
Notes: 1. Only modes 4 and 5 are available on the ROMless version. 2. Flash memory programmer mode information is preliminary. 3. The FWE pin function is only available on the H8S/2318 F-ZTAT and H8S/2315 F-ZTAT versions. The EMLE pin function is only available on the H8S/2319 F-ZTAT version. It cannot be used as a WDTOVF pin on the F-ZTAT version.
12
1.5
Table 1.3
Pin Functions
Pin Functions
Pin No.
Type Power
Symbol VCC
TFP-100B FP-100A I/O 40, 65, 98 42, 67, 100 Input
Name and Function Power supply: For connection to the power supply. All V CC pins should be connected to the system power supply. Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V). Connects to a crystal oscillator. See section 18, in the Hardware Manual, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Connects to a crystal oscillator. The EXTAL pin can also input an external clock. See section 18, in the Hardware Manual, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input.
VSS
7, 18, 31, 49, 68, 88 66
9, 20, 33, 51, 70, 90 68
Input
Clock
XTAL
Input
EXTAL
67
69
Input
o
69
71
Output System clock: Supplies the system clock to an external device.
13
Pin No. Type Symbol TFP-100B FP-100A I/O 61, 58, 57 63, 60, 59 Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2318 Series is operating. * H8S/2318 F-ZTAT, H8S/2315 F-ZTAT versions
Operating mode MD2 to control MD0
Operating FWE MD2 MD1 MD0 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 -- -- -- -- Mode 4 Mode 5 Mode 6 Mode 7 -- -- Mode 10 Mode 11 -- -- Mode 14 Mode 15
14
Pin No. Type Symbol TFP-100B FP-100A I/O 61, 58, 57 63, 60, 59 Input Name and Function * Mask ROM and ROMless versions, and H8S/2319 F-ZTAT version MD1 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 Operating Mode -- -- -- -- Mode 4 Mode 5 Mode 6* Mode 7*
Operating mode MD2 to control MD0
MD2 0
Note: * Not used on ROMless version. System control RES STBY 62 64 64 66 Input Input Reset input: When this pin is driven low, the chip is reset. Standby: When this pin is driven low, a transition is made to hardware standby mode. Bus request: Used by an external bus master to issue a bus request to the H8S/2318 Series.
BREQ
76
78
Input
BREQO
74
76
Output Bus request output: External bus request signal used when an internal bus master accesses external space in the external-bus-released state. Output Bus request acknowledge: Indicates that the bus has been released to an external bus master. Input Input Flash write enable: Enables or disables writing to flash memory. Emulator enable: For connection to ground (0 V).
BACK
75
77
FWE* 1 EMLE * 2
60 60
62 62
15
Pin No. Type Interrupts Symbol NMI TFP-100B FP-100A I/O 63 65 Input Name and Function Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request 7 to 0: These pins request a maskable interrupt.
IRQ7 to IRQ0 Address bus A23 to A0
94, 93, 13, 12, 73 to 76 2, 1, 100, 99, 53 to 50, 48 to 41, 39 to 32 30 to 19, 17 to 14 94 to 97 75, 76 70
96, 95, 15, 14, 75 to 78 4 to 1, 55 to 52, 50 to 43, 41 to 34 32 to 21, 19 to 16 96 to 99 77, 78 72
Input
Output Address bus: These pins output an address.
Data bus Bus control
D15 to D0 CS7 to CS0 AS
I/O
Data bus: These pins constitute a bidirectional data bus.
Output Chip select: Signals for selecting areas 7 to 0. Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Output Read: When this pin is low, it indicates that the external address space can be read. Output High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space.
RD
71
73
HWR
72
74
LWR
73
75
WAIT
74
76
16
Pin No. Type 16-bit timerpulse unit (TPU) Symbol TCLKD to TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TFP-100B FP-100A I/O 6, 4, 2, 1 8, 6, 4, 3 Input Name and Function Clock input D to A: These pins input an external clock. Input capture/ output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/ output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A3 to D3: The TGR3A to TGR3D input capture input or output compare output, or PWM output pins. Input capture/ output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins.
99, 100, 1, 2
1 to 4
I/O
3, 4
5, 6
I/O
TIOCA2, TIOCB2
5, 6
7, 8
I/O
TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4
54 to 56, 59
56 to 58, 61
I/O
89, 90
91, 92
I/O
TIOCA5, TIOCB5
91, 92
93, 94
I/O
8-bit timer
TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1
91, 92 59, 90
93, 94 61, 92
Output Compare match output: The compare match output pins. Input Counter external clock input: Input pins for the external clock input to the counter. Counter external reset input: The counter reset input pins.
56, 89
58, 91 62
Input
Watchdog timer (WDT)
WDTOVF* 3 60
Output Watchdog timer overflows: The counter overflows signal output pin in watchdog timer mode.
17
Pin No. Type Serial communication interface (SCI) Smart Card interface Symbol TxD1, TxD0 RxD1, RxD0 SCK1 SCK0 AN7 to AN0 ADTRG TFP-100B FP-100A I/O 9, 8 11, 10 13, 12 86 to 79 93 11, 10 13, 12 15, 14 88 to 81 95 Name and Function
Output Transmit data (channel 0, 1): Data output pins. Input I/O Input Input Receive data (channel 0, 1): Data input pins. Serial clock (channel 0, 1): Clock I/O pins. Analog 7 to 0: Analog input pins. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion.
A/D converter
D/A converter A/D converter and D/A converters
DA1, DA0 AVCC
86, 85 77
88, 87 79
Output Analog output: D/A converter analog output pins. Input This is the power supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (V CC). This is the ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). This is the reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (V CC). Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 2: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 2 data direction register (P2DDR).
AVSS
87
89
Input
Vref
78
80
Input
I/O ports
P17 to P10
6 to 1, 100, 99
8 to 1
I/O
P27 to P20
92 to 89, 59, 56 to 54
94 to 91, 61, 58 to 56
I/O
18
Pin No. Type I/O ports Symbol P35 to P30 TFP-100B FP-100A I/O 13 to 8 15 to 10 I/O Name and Function Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: An 8-bit input port. Port A* 4: A 4-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). Port B* 4: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). Port C*4: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). Port D*4: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR).
P47 to P40 PA3 to PA0
86 to 79 53 to 50
88 to 81 55 to 52
Input I/O
PB7 to PB0
48 to 41
50 to 43
I/O
PC7 to PC0
39 to 32
41 to 34
I/O
PD7 to PD0
30 to 23
32 to 25
I/O
PE7 to PE0
22 to 19, 17 to 14
24 to 21, 19 to 16
I/O
PF7 to PF0
69 to 76
71 to 78
I/O
PG4 to PG0
97 to 93
99 to 95
I/O
Notes: 1. 2. 3. 4.
Applies to the H8S/2318 F-ZTAT and H8S/2315 F-ZTAT versions only. Applies to the H8S/2319 F-ZTAT version only. Applies to mask ROM and ROMless versions only. Cannot be used as an I/O port on the ROMless versions.
19
1.6
Table 1.4
Product Lineup
H8S/2319, H8S/2318 Series Product Lineup
Model F-ZTAT version HD64F2319 Marking Package (Hitachi Package Code)
Product Type H8S/2319* 1
HD64F2319VTE 100-pin TQFP (TFP-100B) HD64F2319VF 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A)
H8S/2318
Mask ROM version
HD6432318*
2
HD6432318TE HD6432318F
F-ZTAT version
HD64F2318
HD64F2318VTE 100-pin TQFP (TFP-100B) HD64F2318VF 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A)
H8S/2317
Mask ROM version
HD6432317*
2
HD6432317TE HD6432317F
H8S/2316*
1
Mask ROM version
HD6432316
HD6432316TE HD6432316F
H8S/2315*
1
F-ZTAT version
HD64F2315
HD64F2315VTE 100-pin TQFP (TFP-100B) HD64F2315VF 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A) 100-pin TQFP (TFP-100B) 100-pin QFP (FP-100A)
H8S/2313*
1
Mask ROM version
HD6432313
HD6432313TE HD6432313F
H8S/2312
ROMless version
HD6412312
HD6412312VTE HD6412312VF
H8S/2311
Mask ROM version
HD6432311
HD6432311TE HD6432311F
H8S/2310
ROMless version
HD6412310
HD6412310VTE HD6412310VF
Notes: 1. Under development 2. The HD6432318 and HD6432317 include products for V CC = 2.4 V to 3.6 V (low-voltage operation) as well as for VCC = 2.7 V to 3.6 V and VCC = 3.0 V to 3.6 V. For details, see section 7, Electrical Characteristics.
20
1.7
Package Dimensions
Unit: mm
16.0 0.2 14 75 76 51 50
16.0 0.2
100 1 *0.22 0.05 0.20 0.04 25 0.08 M 1.0
26
0.5
*0.17 0.05 0.15 0.04
1.20 Max
1.00
1.0 0 - 8 0.5 0.1
0.10
0.10 0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TFP-100B -- Conforms 0.5 g
Figure 1.4 TFP-100B Package Dimensions
21
24.8 0.4 20 80 81 51 50
Unit: mm
18.8 0.4
100 1 *0.32 0.08 0.30 0.06 30
0.13 M
31
3.10 Max
0.65
*0.17 0.05 0.15 0.04
14
2.4 0.83
0 - 10
0.58
0.20 +0.10 -0.20
2.70
1.2 0.2
Hitachi Code JEDEC EIAJ Weight (reference value) FP-100A -- -- 1.7 g
0.15
*Dimension including the plating thickness Base material dimension
Figure 1.5 FP-100A Package Dimensions
22
Section 2 MCU Operating Modes
2.1
2.1.1
Overview
Operating Mode Selection (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions)
The H8S/2318 Series has eight operating modes (modes 4 to 7, 10, 11, 14 and 15). These modes are determined by the mode pin (MD2 to MD0) and flash write enable pin (FWE) settings. The CPU operating mode and initial bus width can be selected as shown in table 2.1. Table 2.1 lists the MCU operating modes. Table 2.1 MCU Operating Mode Selection (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions)
External Data Bus On-Chip Initial ROM Value -- -- Max. Value --
MCU CPU Operating Operating Mode FWE MD2 MD1 MD0 Mode Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1 0 1 1 0 0 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Advanced User program mode -- -- Advanced Boot mode -- Advanced Expanded mode with on-chip ROM disabled Expanded mode with on-chip ROM enabled Single-chip mode -- -- --
Disabled 16 bits 16 bits 8 bits Enabled 8 bits -- -- -- 16 bits 16 bits -- --
Enabled 8 bits -- -- --
16 bits -- --
Enabled 8 bits --
16 bits --
23
The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2318 Series actually accesses a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. Modes 10, 11, 14, and 15 are boot modes and user program modes in which the flash memory can be programmed and erased. For details, see section 17, ROM, in the Hardware Manual The H8S/2318 Series can only be used in modes 4 to 7, 10, 11, 14, and 15. This means that the flash write enable pin and mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 2.1.2 Operating Mode Selection (Mask ROM, ROMless, and H8S/2319 F-ZTAT Versions)
The H8S/2319 and H8S/2318 Series have four operating modes (modes 4 to 7). The operating mode is determined by the mode pins (MD2 to MD0). The CPU operating mode, enabling or disabling of on-chip ROM, and the initial bus width setting can be selected as shown in table 2.2. Table 2.2 lists the MCU operating modes.
24
Table 2.2
MCU Operating Mode Selection (Mask ROM, ROMless, and H8S/2319 F-ZTAT Versions)
External Data Bus On-Chip Initial ROM Value -- -- Max. Value --
MCU CPU Operating Operating Mode MD2 MD1 MD0 Mode Description 0 1 2 3 4* 5* 6 7 1 1 0 1 0 0 0 1 0 1 0 1 0 1 -- --
Advanced Expanded mode with Disabled 16 bits on-chip ROM disabled 8 bits Expanded mode with on-chip ROM enabled Single-chip mode Enabled 8 bits --
16 bits 16 bits 16 bits --
Note: * Only modes 4 and 5 are provided in the ROMless version.
The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2319 and H8S/2318 Series actually access a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. The H8S/2319 and H8S/2318 Series can only be used in modes 4 to 7. This means that the mode pins must be set to select one of these modes. However, note that only mode 4 or 5 can be set for the ROMless version. Do not change the inputs at the mode pins during operation. 2.1.3 Register Configuration
The H8S/2319 and H8S/2318 Series have a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) and system control register 2 (SYSCR2)*2 that control the operation of the chip. Table 2.3 summarizes these registers.
25
Table 2.3
Name
Registers
Abbreviation MDCR SYSCR
2
R/W R R/W R/W
Initial Value Undefined H'01 H'00
Address* 1 H'FF3B H'FF39 H'FF42
Mode control register System control register System control register 2*
SYSCR2
Notes: 1. Lower 16 bits of the address. 2. The SYSCR2 register can only be used in the F-ZTAT version. In the mask ROM and ROMless versions this register will return an undefined value if read, and cannot be modified.
2.2
2.2.1
Bit
Register Descriptions
Mode Control Register (MDCR)
: 7 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R
Initial value : R/W :
1 --
Note: * Determined by pins MD2 to MD0.
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2318 Series chip. Bit 7--Reserved: This bit is always read as 1, and cannot be modified. Bits 6 to 3--Reserved: These bits are always read as 0, and cannot be modified. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are read-only bits, and cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. 2.2.2
Bit
System Control Register (SYSCR)
: 7 -- 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 LWROD 0 R/W 1 -- 0 R/W 0 RAME 1 R/W
Initial value : R/W :
0 R/W
26
Bit 7--Reserved: Only 0 should be written to this bit. Bit 6--Reserved: This bit is always read as 0, and cannot be modified. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 3.4.1, Interrupt Control Modes and Interrupt Operation, in the Hardware Manual.
Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode Description 0 -- 2 -- Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited (Initial value)
Bit 3--NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value)
Bit 2--LWR Output Disable (LWROD): Enables or disables LWR output.
Bit 2 LWROD 0 1 Description PF3 is designated as LWR output pin PF3 is designated as I/O port, and does not function as LWR output pin (Initial value)
Bit 1--Reserved: Only 0 should be written to this bit. Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value)
27
2.2.3
Bit
System Control Register 2 (SYSCR2) (F-ZTAT Version Only)
: 7 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 FLSHE 0 R/W 2 -- 0 -- 1 -- 0 -- 0 -- 0 --
Initial value : R/W :
0 --
SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 4--Reserved: These bits are always read as 0, and cannot be modified. Bit 3--Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details, see section 17, ROM, in the Hardware Manual.
Bit 3 FLSHE 0 1 Description Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB
Bits 2 to 0--Reserved: These bits are always read as 0, and cannot be modified.
2.3
2.3.1
Operating Mode Descriptions
Modes 1 to 3
Modes 1 to 3 are not supported in the H8S/2319 and H8S/2318 Series, and must not be set. 2.3.2 Mode 4 (Expanded Mode with On-Chip ROM Disabled)
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, ports A, B, and C function as an address bus, ports D and E functions as a data bus, and part of port F carries bus control signals. Pins P13 to P10 function as input ports immediately after a reset. These pins can be set to output addresse by setting the corresponding data direction register (DDR) bits and A23E to A20E in PFCR1 to 1.
28
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 2.3.3 Mode 5 (Expanded Mode with On-Chip ROM Disabled)
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, ports A, B and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. Pins P13 to P10 function as input ports immediately after a reset. These pins can be set to output addresses by setting the corresponding data direction register (DDR) bits and A23E to A20E in PFCR1 to 1. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 2.3.4 Mode 6 (Expanded Mode with On-Chip ROM Enabled)
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, ports A, B, and C function as input ports immediately after a reset. These pins can be set to output addresses by setting the corresponding data direction register (DDR) bits and A23E to A20E in PFCR1 to 1. Port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 2.3.5 Mode 7 (Single-Chip Mode)
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input/output ports. 2.3.6 Modes 8 and 9 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only)
Modes 8 and 9 are not supported in the H8S/2319 and H8S/2318 Series, and must not be set.
29
2.3.7
Mode 10 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only)
This is a flash memory boot mode. For details, see section 17, ROM, in the Hardware Manual. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced expanded mode with on-chip ROM enabled. 2.3.8 Mode 11 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only)
This is a flash memory boot mode. For details, see section 17, ROM, in the Hardware Manual. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced single-chip mode. 2.3.9 Modes 12 and 13 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only)
Modes 12 and 13 are not supported in the H8S/2319 and H8S/2318 Series, and must not be set. 2.3.10 Mode 14 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only)
This is a flash memory user program mode. For details, see section 17, ROM, in the Hardware Manual. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced expanded mode with on-chip ROM enabled. 2.3.11 Mode 15 (H8S/2318 F-ZTAT and H8S/2315 F-ZTAT Versions Only)
This is a flash memory user program mode. For details, see section 17, ROM, in the Hardware Manual. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced single-chip mode.
30
2.4
Pin Functions in Each Operating Mode
The pin functions of ports 1 and A to F vary depending on the operating mode. Table 2.4 shows their functions in each operating mode. Table 2.4 Pin Functions in Each Mode
Mode 6* 2 Mode 10* 3 Mode 14* 3 P* 1/T/A P* 1/A P* /A P* /A D
1 1 1
Port Port 1 Port A Port B Port C Port D Port E Port F PF7 PF6, PF3 PF5, PF4 PF2 to PF0 P13 to P10 PA3 to PA0
Mode 4 P* /T/A A A A D P/D* P/C*
1 1 1
Mode 5 P* 1/T/A A A A D P* /D P/C*
1
Mode 7* 2 Mode 11* 3 Mode 15* 3 P* 1/T P P P P
P* /D P/C*
1
1
P P* 1/C P
P/C* 1 C P* /C
1
P/C* 1 C P* /C
1
P/C* 1 C P* 1/C
Legend P: I/O port T: Timer I/O A: Address bus output D: Data bus I/O C: Control signals, clock I/O Notes: 1. After reset 2. Not used on ROMless version. 3. Applies to H8S/2318 F-ZTAT and H8S/2315 F-ZTAT versions only.
2.5
Memory Map in Each Operating Mode
Figures 2.1 to 2.7 show memory maps for each of the operating modes. The address space is 16 Mbytes. The address space is divided into eight areas.
31
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000
Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000
Mode 7 (advanced single-chip mode) H'000000 On-chip ROM H'010000
External address space
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*5
H'080000 External address space H'FF7400 H'FFDC00 Reserved area*4 On-chip RAM*3
H'080000 External address space H'FF7400 H'FFDC00 H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF Reserved area*4 On-chip RAM*3,*6 External address space Internal I/O registers External address space Internal I/O registers
H'07FFFF
H'FF7400 H'FFDC00 H'FFFBFF H'FFFE50 H'FFFF07
Reserved area*4 On-chip RAM*6
H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF
Internal I/O registers
H'FFFF28 H'FFFFFF
Internal I/O registers
Notes: 1. 2. 3. 4. 5. 6.
External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Do not access the reserved area in addresses H'FF7400 to H'FFDBFF. Do not access the reserved areas. When writing to the flash memory, do not clear the RAME bit in SYSCR to 0 because the on-chip RAM is used in the writing procedure.
Figure 2.1 H8S/2319 F-ZTAT Memory Map in Each Operating Mode
32
Modes 4 and 5*1 (advanced expanded modes with on-chip ROM disabled) H'000000
Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000
Mode 7 (advanced single-chip mode) H'000000
On-chip ROM
On-chip ROM
External address space
H'010000
H'010000
On-chip ROM/ external address space*2
On-chip ROM/ reserved area*3,*5
H'03FFFF H'040000 H'FFDC00 On-chip RAM
*4
External address space H'FFDC00 On-chip RAM
*4
H'FFDC00
On-chip RAM H'FFFBFF
H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF
H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF
External address space Internal I/O registers External address space Internal I/O registers
H'FFFE50 H'FFFF07
Internal I/O registers
H'FFFF28 H'FFFFFF
Internal I/O registers
Notes: 1. 2. 3. 4. 5.
Only modes 4 and 5 are provided in the ROMless version (H8S/2312). External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Do not access the reserved areas.
Figure 2.2 (a) H8S/2318 and H8S/2312 Memory Map in Each Operating Mode
33
Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000
Mode 11 Boot Mode (advanced single-chip mode) H'000000
On-chip ROM
On-chip ROM
H'010000
H'010000
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*4
H'03FFFF H'040000 H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF External address space H'FFDC00 On-chip RAM*3
H'FFFE50 H'FFFF07
Internal I/O registers
H'FFFF28 H'FFFFFF
Internal I/O registers
Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. 4. Do not access the reserved areas.
Figure 2.2 (b) H8S/2318 Memory Map in Each Operating Mode (F-ZTAT Version Only)
34
Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000
Mode 15 User Program Mode (advanced single-chip mode) H'000000
On-chip ROM
On-chip ROM
H'010000
H'010000
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*4
H'03FFFF H'040000 H'FFDC00 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF External address space H'FFDC00 On-chip RAM*3
H'FFFE50 H'FFFF07
Internal I/O registers
H'FFFF28 H'FFFFFF
Internal I/O registers
Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 3. On-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. 4. Do not access the reserved areas.
Figure 2.2 (c) H8S/2318 Memory Map in Each Operating Mode (F-ZTAT Version Only)
35
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000
Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000
Mode 7 (advanced single-chip mode) H'000000
On-chip ROM
On-chip ROM
External address space
H'010000 On-chip ROM/ external address space*1
H'010000 On-chip ROM/ reserved area*2,*4
H'020000 Reserved area*4/external address space*1
H'020000 Reserved area*4 H'03FFFF
H'040000 H'FFDC00 On-chip RAM*3 H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00
External address space H'FFDC00 On-chip RAM*3 H'FFFBFF External address space Internal I/O registers External address space Internal I/O registers On-chip RAM
H'FFFE50 H'FFFF07
Internal I/O registers
H'FFFF28 H'FFFFFF
Internal I/O registers
Notes: 1. 2. 3. 4.
External addresses when EAE = 1 in BCRL; on-chip ROM or reserved area when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Do not access the reserved areas.
Figure 2.3 H8S/2317 Memory Map in Each Operating Mode
36
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000
Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000
Mode 7 (advanced single-chip mode) H'000000
On-chip ROM
On-chip ROM
External address space
H'010000
H'010000
Reserved area*3/ external address space*1
Reserved area*3
H'03FFFF H'040000 H'FFDC00 On-chip RAM
*2
External address space H'FFDC00 On-chip RAM
*2
H'FFDC00
On-chip RAM H'FFFBFF
H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF
H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF
External address space Internal I/O registers External address space Internal I/O registers
H'FFFE50 H'FFFF07
Internal I/O registers
H'FFFF28 H'FFFFFF
Internal I/O registers
Notes: 1. External addresses when EAE = 1 in BCRL; reserved area when EAE = 0. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 3. Do not access the reserved areas.
Figure 2.4 H8S/2316 Memory Map in Each Operating Mode
37
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000
Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000
Mode 7 (advanced single-chip mode) H'000000 On-chip ROM H'010000
External address space
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*5
H'060000 H'080000
Reserved area*4
H'060000 H'080000
Reserved area*4
H'060000 H'07FFFF
Reserved area*4
External address space
External address space
H'FFDC00
On-chip RAM*3
H'FFDC00 H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF
On-chip RAM*3 External address space Internal I/O registers External address space Internal I/O registers
H'FFDC00 H'FFFBFF H'FFFE50 H'FFFF07
On-chip RAM
H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF
Internal I/O registers
H'FFFF28 H'FFFFFF
Internal I/O registers
Notes: 1. 2. 3. 4. 5.
External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Do not access the reserved area in addresses H'060000 to H'07FFFF. Do not access the reserved areas.
Figure 2.5 (a) H8S/2315 F-ZTAT Memory Map in Each Operating Mode
38
Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000
Mode 11 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*5
H'060000 H'080000
Reserved area*4
H'060000 H'07FFFF
Reserved area*4
External address space
H'FFDC00
On-chip RAM*3
H'FFDC00 H'FFFBFF H'FFFE50 H'FFFF07
On-chip RAM*3
H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF
Internal I/O registers
H'FFFF28 H'FFFFFF
Internal I/O registers
Notes: 1. 2. 3. 4. 5.
External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Do not access the reserved area in addresses H'060000 to H'07FFFF. Do not access the reserved areas.
Figure 2.5 (b) H8S/2315 F-ZTAT Memory Map in Each Operating Mode
39
Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000
Mode 15 User Program Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000
On-chip ROM/ external address space*1
On-chip ROM/ reserved area*2,*5
H'060000 H'080000
Reserved area*4
H'060000 H'07FFFF
Reserved area*4
External address space
H'FFDC00
On-chip RAM*3
H'FFDC00 H'FFFBFF H'FFFE50 H'FFFF07
On-chip RAM*3
H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF
Internal I/O registers
H'FFFF28 H'FFFFFF
Internal I/O registers
Notes: 1. 2. 3. 4. 5.
External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. Reserved area when EAE = 1 in BCRL; on-chip ROM when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Do not access the reserved area in addresses H'060000 to H'07FFFF. Do not access the reserved areas.
Figure 2.5 (c) H8S/2315 F-ZTAT Memory Map in Each Operating Mode
40
Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000
Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000
Mode 7 (advanced single-chip mode) H'000000
On-chip ROM
On-chip ROM
External address space
H'010000
H'010000
Reserved area*3/ external address space*1
Reserved area*3
H'03FFFF H'040000 H'FFDC00 H'FFF400 On-chip RAM*2 H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00 H'FFF400 On-chip RAM*2 External address space Internal I/O registers External address space Internal I/O registers External address space Reserved area*3 H'FFDC00 H'FFF400 H'FFFBFF On-chip RAM Reserved area*3
Reserved area*3
H'FFFE50 H'FFFF07
Internal I/O registers
H'FFFF28 H'FFFFFF
Internal I/O registers
Notes: 1. External addresses when EAE = 1 in BCRL; reserved area when EAE = 0. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. 3. Do not access the reserved areas.
Figure 2.6 H8S/2313 Memory Map in Each Operating Mode
41
Modes 4 and 5*1 (advanced expanded modes with on-chip ROM disabled) H'000000
Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000
Mode 7 (advanced single-chip mode) H'000000
On-chip ROM
On-chip ROM
H'008000 Reserved area*4
H'008000 Reserved area*4
External address space
H'010000
H'010000
Reserved area*4/ external address space*2
Reserved area*4
H'03FFFF H'040000 H'FFDC00 H'FFF400 On-chip RAM*3 H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF H'FFDC00 H'FFF400 On-chip RAM*3 External address space Internal I/O registers External address space Internal I/O registers External address space Reserved area*4 H'FFDC00 H'FFF400 H'FFFBFF On-chip RAM Reserved area*4
Reserved area*4
H'FFFE50 H'FFFF07
Internal I/O registers
H'FFFF28 H'FFFFFF
Internal I/O registers
Notes: 1. 2. 3. 4.
Only modes 4 and 5 are provided in the ROMless version (H8S/2310). External addresses when EAE = 1 in BCRL; reserved area when EAE = 0. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Do not access the reserved areas.
Figure 2.7 H8S/2311 and H8S/2310 Memory Map in Each Operating Mode
42
Section 3 Exception Handling and Interrupt Controller
3.1
3.1.1
Overview
Exception Handling Types and Priority
As table 3.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 3.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits in SYSCR. For details of exception handling and the interrupt controller, see section 2, Exception Handling, and section 3, Interrupt Controller, in the Hardware Manual. Table 3.1
Priority High
Exception Types and Priority
Exception Type Reset Trace* 1 Interrupt Trap instruction* 3 (TRAPA) Start of Exception Handling Starts after a low-to-high transition at the RES pin, or when the watchdog timer overflows Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued* 2 Started by execution of a trap instruction (TRAPA)
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in the program execution state.
43
3.2
3.2.1
Interrupt Controller
Interrupt Controller Features
* Two interrupt control modes Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with IPRs Interrupt priority registers (IPRs) are provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Nine external interrupt pins NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected independently for IRQ7 to IRQ0. * DTC control DTC activation is controlled by means of interrupts. 3.2.2 Table 3.2
Name Nonmaskable interrupt
Pin Configuration Interrupt Controller Pins
Symbol NMI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected
External interrupt requests 7 to 0
IRQ7 to IRQ0
Input
44
3.3
Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (43 sources). 3.3.1 External Interrupts
There are nine external interrupts: NMI and IRQ7 to IRQ0. NMI and IRQ7 to IRQ0 can be used to restore the chip from software standby mode. (IRQ7 to IRQ3 can be used as software standby mode clearing sources by setting the IRQ37S bit in SBYCR to 1.) NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. Interrupts IRQ7 to IRQ0: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. * Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. * The interrupt priority level can be set with the IPR registers. * The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 3.1.
IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit S R Clear signal Note: n = 7 to 0
IRQnE
Q
IRQn interrupt request
IRQn input
Figure 3.1 Block Diagram of Interrupts IRQ7 to IRQ0
45
Figure 3.2 shows the timing of IRQnF setting.
o
IRQn input pin
IRQnF
Figure 3.2 Timing of IRQnF Setting The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. When a pin is used as an external interrupt input pin, clear the corresponding DDR bit to 0 and do not use the pin as an I/O pin for another function. 3.3.2 Internal Interrupts
There are 43 sources for internal interrupts from on-chip supporting modules. 1. For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If any one of these is set to 1, an interrupt request is issued to the interrupt controller. 2. The interrupt priority level can be set by means of the IPR registers. 3. The DTC can be activated by a TPU, SCI, or other interrupt request. When the DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect. 3.3.3 Interrupt Exception Vector Table
Table 3.3 shows interrupt sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. The DTC can be activated by an interrupt request. Priorities among modules can be set by means of the IPR registers. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 3.3.
46
Table 3.3
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of Interrupt Source Vector Number 0 1 2 3 4 Vector Address* H'0000 H'0004 H'0008 H'000C H'0010 H'0014 H'0018 H'001C H'0020 H'0024 H'0028 H'002C H'0030 H'0034 H'0038 H'003C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C IPRC6 to IPRC4 Low IPRB2 to IPRB0 IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB6 to IPRB4 DTC Priority Activation High --
Interrupt Source Power-on reset Reserved Reserved for system use
IPR --
Trace Reserved for system use NMI Trap instruction (4 sources) External pin
5 6 7 8 9 10 11
Reserved for system use
12 13 14 15
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
External pin
16 17 18 19 20 21 22 23
47
Interrupt Source
Origin of Interrupt Source
Vector Number 24
Vector Address* H'0060
IPR
DTC Priority Activation
SWDTEND (software- DTC activated data transfer end) WOVI (interval timer) Reserved Reserved ADI (A/D conversion end) Reserved
IPRC2 to High IPRC0 IPRD6 to IPRD4 IPRD2 to IPRD0 IPRE6 to IPRE4 IPRE2 to IPRE0 -- -- -- --
Watchdog timer 25 -- -- A/D -- 26 27 28 29 30 31
H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080
TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) Reserved
TPU channel 0
32
IPRF6 to IPRF4
33
H'0084
34
H'0088
35
H'008C
36 -- 37 38 39
H'0090 H'0094 H'0098 H'009C Low
-- --
48
Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1)
Origin of Interrupt Source TPU channel 1
Vector Number 40
Vector Address* H'00A0
IPR IPRF2 to IPRF0
DTC Priority Activation High
41
H'00A4
42
H'00A8
--
TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow 3) Reserved -- TPU channel 3 TPU channel 2
43 44
H'00AC H'00B0 IPRG6 to IPRG4
--
45
H'00B4
46 47 48
H'00B8 H'00BC H'00C0 IPRG2 to IPRG0
-- --
49
H'00C4
50
H'00C8
51
H'00CC
52 53 54 55
H'00D0 H'00D4 H'00D8 H'00DC Low
-- --
49
Interrupt Source TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5) CMIA0 (compare match A) CMIB0 (compare match B) OVI0 (overflow 0) Reserved CMIA1 (compare match A) CMIB1 (compare match B) OVI1 (overflow 1) Reserved
Origin of Interrupt Source TPU channel 4
Vector Number 56
Vector Address* H'00E0
IPR
DTC Priority Activation
IPRH6 to High IPRH4
57
H'00E4
58 59 TPU channel 5 60
H'00E8 H'00EC H'00F0 IPRH2 to IPRH0
-- --
61
H'00F4
62 63 8-bit timer channel 0 64 65 66 -- 8-bit timer channel 1 67 68 69 70 -- 71
H'00F8 H'00FC H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C Low IPRI2 to IPRI0 IPRI6 to IPRI4
-- --
-- --
-- --
50
Interrupt Source Reserved
Origin of Interrupt Source --
Vector Number 72 73 74
Vector Address* H'0120 H'0124 H'0128
IPR IPRJ6 to IPRJ4
DTC Priority Activation High --
75 76 77 78 79 ERI0 (receive error 0) RXI0 (receive-data-full 0) TXI0 (transmit-dataempty 0) TEI0 (transmit end 0) ERI1 (receive error 1) RXI1 (receive-data-full 1) TXI1 (transmit-dataempty 1) TEI1 (transmit end 1) Reserved -- SCI channel 1 SCI channel 0 80 81 82 83 84 85 86 87 88 89 90 91 Note: * Lower 16 bits of the start address.
H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C Low IPRK2 to IPRK0 -- -- IPRK6 to IPRK4 -- -- IPRJ2 to IPRJ0 --
51
3.4
Interrupt Control Modes and Interrupt Operation
Interrupt operations in the H8S/2319 and H8S/2318 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bit is set to 1 are controlled by the interrupt controller. The interrupt control modes are shown in table 3.4, the interrupts selected in each interrupt control mode in tables 3.5 and 3.6, and operations and control signal functions in each interrupt control mode in table 3.7. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in the IPR registers, and the masking state indicated by the I bit in the CPU's CCR and bits I2 to I0 in EXR. Table 3.4
Interrupt Control Mode 0 -- 2 1
Interrupt Control Modes
Priority Setting Interrupt Registers Mask Bits Description -- -- IPR I -- I2 to I0 Interrupt mask control is performed by the I bit. Setting prohibited 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR.
INTM1 0
INTM0 0 1 0
--
1
--
--
Setting prohibited
Table 3.5
Interrupts Selected in Each Interrupt Control Mode (1)
Interrupt Mask Bits I 0 1 Selected Interrupts All interrupts NMI interrupts All interrupts
Interrupt Control Mode 0
2 *: Don't care
*
52
Table 3.6
Interrupts Selected in Each Interrupt Control Mode (2)
Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt with priority level greater than the mask level (IPR > I2 to I0)
Interrupt Control Mode 0 2
Table 3.7
Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt Acceptance Control I IM x --*
1
Interrupt Control Mode 0 2
Settings INTM1 INTM0 0 1 0 0
8-Level Control I2 to I0 IPR x -- IM --* 2 PR
Default Priority T Determination (Trace) -- T
Legend : Interrupt operation control performed x: No operation (all interrupts enabled) IM: Used as interrupt mask bit PR: Sets priority --: Not used Notes: 1. Set to 1 when interrupt is accepted. 2. Keep the initial setting.
53
3.5
Interrupt Response Times
The H8S/2319 and H8S/2318 Series are capable of fast word access to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling highspeed processing. Table 3.8 shows interrupt response times--the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution phase symbols used in table 3.8 are explained in table 3.9. Table 3.8 Interrupt Response Times
Advanced Mode No. 1 2 3 4 5 6 Execution Phase Interrupt priority determination*
1
INTM1 = 0 3 1 to (19 + 2 SI) 2 SK 2 SI 2 SI
4
INTM1 = 1 3 1 to (19 + 2 SI) 3 SK 2 SI 2 SI 2 13 to 33
Number of wait states until executing instruction ends* 2 PC, CCR, and EXR stacking Vector fetch Instruction fetch*
3
Internal processing*
2 12 to 32
Total (when using on-chip memory) Notes: 1. 2. 3. 4.
Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 3.9
Number of States in Interrupt Handling Routine Execution Phases
Access To External Device 8-Bit Bus 16-Bit Bus 2-State Access 2 3-State Access 3+m
Symbol Instruction fetch SI Branch address read SJ Stack manipulation S K
Internal Memory 1
2-State Access 4
3-State Access 6 + 2m
Legend m: Number of wait states in an external device access
54
3.6
3.6.1
DTC Activation by Interrupt
Overview
In the H8S/2319 and H8S/2318 Series, the DTC can be activated by an interrupt. In this case, the following options are available: 1. Interrupt request to CPU 2. Activation request to DTC 3. Selection of a number of the above See table 3.3 for the interrupt requests that can be used to activate the DTC. For details, see section 6, Data Transfer Controller, in the Hardware Manual. 3.6.2 Block Diagram
Figure 3.3 shows a block diagram of the DTC and interrupt controller.
IRQ interrupt
Interrupt request Selection circuit Select signal Clear signal DTCER
DTC activation request vector number
Control logic Clear signal
DTC
On-chip supporting module
Interrupt source clear signal
DTVECR SWDTE clear signal
CPU interrupt request vector number Priority determination I, I2 to I0 CPU
Interrupt controller
Figure 3.3 Interrupt Control for DTC
55
3.6.3
Operation
The interrupt controller has three main functions in DTC control, as described below. Selection of Interrupt Source: For interrupt sources, it is possible to select DTC activation request or CPU interrupt request with the DTCE bit in DTC registers DTCERA to DTCERE. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit in the DTC's MRB register. When the DTC has performed the specified number of data transfers and the transfer counter value is 0, the DTCE bit is cleared to 0 after the DTC data transfer and an interrupt request is sent to the CPU. Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See table 3.10, Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs, for the respective priorities.
56
Table 3.10 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of Interrupt Source Software Vector Number DTVECR Vector Address H'0400 + (DTVECR [6:0]<<1) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0438 H'0440 H'0442 H'0444 H'0446 H'0450 H'0452 H'0458 H'045A
Interrupt Source Write to DTVECR
DTCE* --
Priority High
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 ADI (A/D conversion end) TGI0A (GR0A compare match/input capture) TGI0B (GR0B compare match/input capture) TGI0C (GR0C compare match/input capture) TGI0D (GR0D compare match/input capture) TGI1A (GR1A compare match/input capture) TGI1B (GR1B compare match/input capture) TGI2A (GR2A compare match/input capture) TGI2B (GR2B compare match/input capture)
External pin
16 17 18 19 20 21 22 23
DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 Low
A/D TPU channel 0
28 32 33 34 35
TPU channel 1
40 41
TPU channel 2
44 45
57
Interrupt Source TGI3A (GR3A compare match/input capture) TGI3B (GR3B compare match/input capture) TGI3C (GR3C compare match/input capture) TGI3D (GR3D compare match/input capture) TGI4A (GR4A compare match/input capture) TGI4B (GR4B compare match/input capture) TGI5A (GR5A compare match/input capture) TGI5B (GR5B compare match/input capture) CMIA0 CMIB0 CMIA1 CMIB1 RXI0 (receive-data-full 0) TXI0 (transmit-data-empty 0) RXI1 (receive-data-full 1) TXI1 (transmit-data-empty 1)
Origin of Interrupt Source TPU channel 3
Vector Number 48 49 50 51
Vector Address H'0460 H'0462 H'0464 H'0466 H'0470 H'0472 H'0478 H'047A H'0480 H'0482 H'0488 H'048A H'04A2 H'04A4 H'04AA H'04AC
DTCE* DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE3 DTCEE2 DTCEE1 DTCEE0
Priority High
TPU channel 4
56 57
TPU channel 5
60 61
8-bit timer channel 0 8-bit timer channel 1 SCI channel 0 SCI channel 1
64 65 68 69 81 82 85 86
Low
Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 3.11 summarizes interrupt source selection and interrupt source clearance control according to the setting of the DTCE bit of DTC registers DTCERA to DTCERE and the DISEL bit in the DTC's MRB register.
58
Table 3.11 Interrupt Source Selection and Clearing Control
Settings DTC DTCE 0 1 DISEL * 0 1 Legend : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X: The relevant bit cannot be used. *: Don't care Interrupt Source Selection/Clearing Control DTC X X CPU
Usage Note: SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register, and are not dependent on the DISEL bit.
59
60
Section 4 Bus Controller
4.1 Overview
The H8S/2319 and H8S/2318 Series have an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters--the CPU and data transfer controller (DTC). 4.1.1 Features
The features of the bus controller are listed below. * Manages external address space in area units In advanced mode, manages the external space as 8 areas of 2 Mbytes Bus specifications can be set independently for each area Burst ROM interfaces can be set * Basic bus interface Chip select signals (CS0 to CS7) can be output for areas 0 to 7 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * Burst ROM interface Burst ROM interface can be set for area 0 Selection of 1- or 2-state burst access * Idle cycle insertion An idle cycle can be inserted in case of external read cycles in different areas An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC * Other features External bus release function
61
4.1.2
Block Diagram
CS0 to CS7 Area decoder
Internal address bus
ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK BREQO Internal data bus Bus controller Internal control signals
Bus mode signal
WAIT
Wait controller
WCRH WCRL
CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal
Figure 4.1 Block Diagram of Bus Controller
62
4.1.3
Pin Configuration
Table 4.1 summarizes the pins of the bus controller. Table 4.1
Name Address strobe Read High write
Bus Controller Pins
Symbol AS RD HWR I/O Output Output Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Strobe signal indicating that area 0 is selected. Strobe signal indicating that area 1 is selected. Strobe signal indicating that area 2 is selected. Strobe signal indicating that area 3 is selected. Strobe signal indicating that area 4 is selected. Strobe signal indicating that area 5 is selected. Strobe signal indicating that area 6 is selected. Strobe signal indicating that area 7 is selected. Wait request signal when accessing external 3state access space. Request signal for release of bus to external device. Acknowledge signal indicating that bus has been released. External bus request signal used when internal bus master accesses external space when external bus is released.
Low write
LWR
Output
Chip select 0 Chip select 1 Chip select 2 Chip select 3 Chip select 4 Chip select 5 Chip select 6 Chip select 7 Wait Bus request Bus request acknowledge Bus request output
CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 WAIT BREQ BACK BREQO
Output Output Output Output Output Output Output Output Input Input Output Output
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4.1.4
Register Configuration
Table 4.2 summarizes the registers of the bus controller. Table 4.2 Bus Controller Registers
Initial Value Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL R/W R/W R/W R/W R/W R/W R/W Reset H'FF/H'00* 2 H'FF H'FF H'FF H'D0 H'3C Address* 1 H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5
Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode.
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4.2
4.2.1
Bit
Register Descriptions
Bus Width Control Register (ABWCR)
: 7 ABW7 6 ABW6 5 ABW5 4 ABW4 3 ABW3 2 ABW2 1 ABW1 0 ABW0
Modes 5 to 7 Initial value : R/W Mode 4 Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W : 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W
ABWCR is an 8-bit readable/writable register that designates each area as either 8-bit access space or 16-bit access space. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. After a reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5 to 7*, and to H'00 in mode 4. It is not initialized in software standby mode. Note: * Modes 6 and 7 cannot be used in the ROMless version. Bits 7 to 0--Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space.
Bit n ABWn 0 1 (n = 7 to 0) Description Area n is designated for 16-bit access Area n is designated for 8-bit access
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4.2.2
Bit
Access State Control Register (ASTCR)
: 7 AST7 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W
Initial value : R/W :
1 R/W
ASTCR is an 8-bit readable/writable register that designates each area as either 2-state access space or 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a reset, and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. Wait state insertion is enabled or disabled at the same time.
Bit n ASTn 0 Description Area n is designated for 2-state access Wait state insertion in area n external space access is disabled 1 (n = 7 to 0) Area n is designated for 3-state access Wait state insertion in area n external space access is enabled (Initial value)
4.2.3
Wait Control Registers H and L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in on-chip memory or internal I/O register access. WCRH and WCRL are initialized to H'FF by a reset, and in hardware standby mode. They are not initialized in software standby mode.
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WCRH
Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W
Bits 7 and 6--Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1.
Bit 7 W71 0 Bit 6 W70 0 1 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value)
Bits 5 and 4--Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1.
Bit 5 W61 0 Bit 4 W60 0 1 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value)
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Bits 3 and 2--Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1.
Bit 3 W51 0 Bit 2 W50 0 1 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value)
Bits 1 and 0--Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1.
Bit 1 W41 0 Bit 0 W40 0 1 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value)
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WCRL
Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W
Bits 7 and 6--Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Bit 7 W31 0 Bit 6 W30 0 1 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value)
Bits 5 and 4--Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1.
Bit 5 W21 0 Bit 4 W20 0 1 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value)
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Bits 3 and 2--Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1.
Bit 3 W11 0 Bit 2 W10 0 1 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value)
Bits 1 and 0--Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1.
Bit 1 W01 0 Bit 0 W00 0 1 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value)
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4.2.4
Bit
Bus Control Register H (BCRH)
: 7 ICIS1 6 ICIS0 1 R/W 5 4 3 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W
BRSTRM BRSTS1 BRSTS0 0 R/W 1 R/W 0 R/W
Initial value : R/W :
1 R/W
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH is initialized to H'D0 by a reset, and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas.
Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas. Idle cycle inserted in case of successive external read cycles in different areas. (Initial value)
Bit 6--Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed .
Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles. Idle cycle inserted in case of successive external read and external write cycles. (Initial value)
Bit 5--Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface area.
Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface area Area 0 is burst ROM interface area (Initial value)
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Bit 4--Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface.
Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value)
Bit 3--Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst access on the burst ROM interface.
Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value)
Bits 2 to 0--Reserved: Only 0 should be written to these bits. 4.2.5
Bit
Bus Control Register L (BCRL)
: 7 BRLE 6 BREQOE 0 R/W 5 EAE 1 R/W 4 -- 1 R/W 3 -- 1 R/W 2 -- 1 R/W 1 -- 0 R/W 0 WAITE 0 R/W
Initial value : R/W :
0 R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, selection of the area partition unit, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a reset, and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7 BRLE 0 1 Description External bus release disabled. BREQ, BACK, and BREQO pins can be used as I/O ports (Initial value) External bus release enabled
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Bit 6--BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus-released state or when an internal bus master performs an external space access.
Bit 6 BREQOE 0 1 Description BREQO output disabled. BREQO pin can be used as I/O port BREQO output enabled (Initial value)
Bit 5--External Address Enable (EAE): Designates addresses H'010000 to H'03FFFF* as either internal or external addresses. Note: * H'010000 to H'05FFFF in the H8S/2315. H'010000 to H'07FFFF in the H8S/2319.
Description Bit 5 EAE 0 H8S/2319, H8S/2318, H8S/2315 H8S/2317 On-chip ROM Addresses H'010000 to H'01FFFF are on-chip ROM and addresses H'020000 to H'03FFFF are reserved area* 1 H8S/2316, H8S/2313, H8S/2311 Reserved area* 1
1
Addresses H'010000 to H'03FFFF* 2 are external addresses in external expanded mode or reserved area* 1 in single-chip mode
Notes: 1. Do not access a reserved area. 2. H'010000 to H'05FFFF in the H8S/2315. H'010000 to H'07FFFF in the H8S/2319.
Bits 4 to 2--Reserved: Only 1 should be written to these bits. Bit 1--Reserved: Only 0 should be written to this bit. Bit 0--WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin.
Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port Wait input by WAIT pin enabled (Initial value)
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4.3
4.3.1
Overview of Bus Control
Area Partitioning
In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. Figure 4.2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area.
H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF Advanced mode
Figure 4.2 Area Partitioning
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4.3.2
Bus Specifications
The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is always set. When the burst ROM interface is selected, 16-bit bus mode is always set. Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. With the burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 4.3 shows the bus specifications for each basic bus interface area.
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Table 4.3
ABWCR ABWn 0
Bus Specifications for Each Area (Basic Bus Interface)
ASTCR ASTn 0 1 WCRH, WCRL Wn1 -- 0 Wn0 -- 0 1 1 0 1 Bus Specifications (Basic Bus Interface) Bus Width 16 Access States 2 3 Program Wait States 0 0 1 2 3 8 2 3 0 0 1 2 3
1
0 1
-- 0
-- 0 1
1
0 1
4.3.3
Memory Interfaces
The memory interfaces of the H8S/2319 and H8S/2318 Series comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; and a burst ROM interface that allows direct connection of burst ROM(only area 0). An area for which the basic bus interface is designated functions as normal space, and an area for which the burst ROM interface is designated functions as burst ROM space. 4.3.4 Advanced Mode
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (4.4 and 4.5) should be referred to for further details. Area 0: Area 0 includes on-chip ROM, and in expanded mode with on-chip ROM disabled, all of area 0 is external space. In expanded mode with on-chip ROM enabled, the space excluding onchip ROM is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. Areas 1 to 6: In external expanded mode, all of area 1 to area 6 is external space.
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When area 1 to 6 external space is accessed, the CS1 to CS6 pin signals can be output, respectively. Only the basic bus interface can be used for areas 1 to 6. Area 7: Area 7 includes the on-chip RAM and internal/O registers. In external expanded mode, the space excluding the on-chip RAM and internal/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. 4.3.5 Chip Select Signals
The chip can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 4.3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of CSn signal output is performed by setting the data direction register (DDR) bit for the port corresponding to the particular CSn pin. In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a reset. Pins CS1 to CS7 are placed in the input state after a reset, and so the corresponding DDR bits should be set to 1 when outputting signals CS1 to CS7. In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state after a reset, and so the corresponding DDR bits should be set to 1 when outputting signals CS0 to CS7. For details, see section 5, I/O Ports.
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Bus cycle T1 o Address bus CSn T2 T3
Area n external address
Figure 4.3 CSn Signal Output Timing (n = 0 to 7)
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4.4
4.4.1
Basic Bus Interface
Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL. For details, see section 4.4, Basic Bus Interface, in the Hardware Manual. 4.4.2 Wait Control
When accessing external space , the chip can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings in WCRH and WCRL. Pin Wait Insertion: Setting the WAITE bit in BCRL to 1 enables wait input by means of the WAIT pin. When external space is accessed in this state, a program wait is first inserted in accordance with the settings in WCRH and WCRL. If the WAIT pin is low at the falling edge of o in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. Figure 4.4 shows an example of wait state insertion timing.
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By program wait T1 o T2 Tw
By WAIT pin Tw Tw T3
WAIT Address bus AS
RD Read Data bus Read data
HWR, LWR Write Data bus Write data
Note: Downward arrows indicates the timing of WAIT pin sampling.
Figure 4.4 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled.
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4.5
4.5.1
Burst ROM Interface
Overview
With the H8S/2319 and H8S/2318 Series, external space area 0 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space interface enables 16-bit ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum or 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 4.5.2 Basic Timing
The number of states in the initial cycle (full access) of the burst ROM interface is determined by the setting of the AST0 bit in ASTCR. When the AST0 bit is set to 1, wait state insertion is also possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it functions as 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 4.5 (a) and (b). The timing shown in figure 4.5 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 4.5 (b) is for the case where both these bits are cleared to 0.
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Full access T1 o T2 T3 T1
Burst access T2 T1 T2
Address bus
Only lower address changed
CS0
AS
RD
Data bus
Read data
Read data
Read data
Figure 4.5 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1= 1)
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Full access T1 o T2
Burst access T1 T1
Address bus
Only lower address changed
CS0
AS
RD
Data bus
Read data
Read data Read data
Figure 4.5 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 4.5.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 4.4.2, Wait Control. Wait states cannot be inserted in a burst cycle.
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4.6
4.6.1
Idle Cycle
Operation
When the H8S/2319 or H8S/2318 Series chip accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses in different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and so on. Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is enabled in advanced mode. Figure 4.6 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A T1 o Address bus CS (area A) CS (area B) RD Data bus T2 T3
Bus cycle B T1 T2
Bus cycle A T1 o Address bus
CS (area A)
Bus cycle B TI T1 T2
T2
T3
(a) Idle cycle not inserted (ICIS1 = 0)
;
CS (area B) RD Data bus Data collision (b) Idle cycle inserted (ICIS1 = 1 (initial value))
Long output floating time
Figure 4.6 Example of Idle Cycle Operation (1)
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Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 4.7 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A T1 o
Address bus CS (area A) CS (area B) RD HWR Data bus
Bus cycle B T1 T2
o Address bus CS (area A) CS (area B)
Bus cycle A T1 T2 T3
Bus cycle B TI T1 T2
T2
T3
Long output floating time (a) Idle cycle not inserted (ICIS0 = 0)
;
RD HWR Data bus Data collision (b) Idle cycle inserted (ICIS0 = 1 (initial value))
Figure 4.7 Example of Idle Cycle Operation (2)
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Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 4.8. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set.
Bus cycle A T1 o
Address bus CS (area A) CS (area B) RD
Bus cycle B T1 T2
o Address bus CS (area A) CS (area B) RD
Bus cycle A T1 T2 T3
Bus cycle B TI T1 T2
T2
T3
Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (ICIS1 = 1 (initial value))
Figure 4.8 Relationship between Chip Select (CS) and Read (RD)
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4.6.2
Pin States in Idle Cycle
Table 4.4 shows the pin states in an idle cycle. Table 4.4
Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR
Pin States in Idle Cycle
Pin State Contents of following bus cycle High impedance High High High High High
4.7
4.7.1
Bus Release
Overview
The H8S/2319 and H8S/2318 Series can release the external bus in response to a bus request from an external device. In the external bus-released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus-released state, it can issue a request off-chip for the bus request to be dropped. 4.7.2 Operation
In external expanded mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2319 or H8S/2318 Series chip. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the highimpedance state, establishing the external bus-released state. In the external bus-released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped.
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If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external access in the external bus-released state, the BREQO pin is driven low and a request can be made off-chip to drop the bus request. When the BREQ pin goes high, the BACK pin is driven high at the prescribed timing and the external bus-released state is terminated. If an external bus release request and external access occur simultaneously, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) 4.7.3 Pin States in External-Bus-Released State
Table 4.5 shows pin states in the external-bus-released state. Table 4.5
Pins A23 to A0 D15 to D0 CSn AS RD HWR LWR
Pin States in Bus-Released State
Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance
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4.7.4
Transition Timing
Figure 4.9 shows the timing for transition to the bus-released state.
CPU cycle T0 o High impedance T1 T2 External-bus-released state CPU cycle
Address bus Data bus
Address
High impedance
AS
High impedance
RD HWR, LWR BREQ
High impedance
High impedance
BACK
BREQO*
Minimum 1 state [1] [2] [3] [4] [5] [6]
[1] [2] [3] [4] [5] [6]
Low level of BREQ pin is sampled at fall of T2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external-bus-released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. BREQO signal goes high 1.5 clocks after rise of BACK signal.
Note: * Output only when BREQOE = 1.
Figure 4.9 Bus-Released State Transition Timing
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4.7.5
Usage Note
If MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function will halt. Therefore, these settings should not be used.
4.8
4.8.1
Bus Arbitration
Overview
The H8S/2319 and H8S/2318 Series have a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 4.8.2 Operation
The bus arbiter monitors the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DTC > CPU (Low) An external access by an internal bus master and external bus release can be executed in parallel. If an external bus release request and an external access by an internal bus master occur simultaneously, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) 4.8.3 Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus.
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CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. For details of times when the bus is not transferred, see appendix A.5, Bus States During Instruction Execution, in the Hardware Manual. * If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 4.8.4 Note on Use of External Bus Release
External bus release can be performed on completion of an external bus cycle. The RD signal remain low until the end of the external bus cycle. Therefore, when external bus release is performed, the RD signals may change from the low level to the high-impedance state.
4.9
Bus Controller Operation in a Reset
In a reset, the chip, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted.
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Section 5 I/O Ports
5.1 Overview
The H8S/2319 and H8S/2318 Series have 10 I/O ports (ports 1, 2, 3, and A to G), and one inputonly port (port 4). Table 5.1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only ports), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. Ports A to E have a built-in MOS pull-up function, and in addition to DR and DDR, have a MOS input pull-up control register (PCR) to control the on/off state of MOS input pull-up. Port 3 and port A include an open drain control register (ODR) that controls the on/off state of the output buffer PMOS. Ports 1, A to F can drive a single TTL load and 50 pF capacitive load, and ports 2, 3, and G can drive a single TTL load and 30 pF capacitive load. Ports 1, 2, and ports 34, 35 (only when used as IRQ inputs), ports F0 to F3 (only when used as IRQ inputs), ports G0 and G1 (only when used as IRQ inputs) are schmitt-triggered inputs.
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Table 5.1
Port
Port Functions
Pins P17/TIOCB2/TCLKD P16/TIOCA2 P15/TIOCB1/TCLKC P14/TIOCA1 Mode 4 Mode 5 Mode 6*1 Mode 7*1
Description
Port 1 * 8-bit I/O port * Schmitttriggered input
8-bit I/O port also functioning as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2)
P13/TIOCD0/TCLKB/A23 When DDR = 0: input port also functioning P12/TIOCC0/TCLKA/A22 as TPU I/O pins (TCLKA, TCLKB, P11/TIOCB0/A21 TIOCA0, TIOCB0, TIOCC0, TIOCD0) P10/TIOCA0/A20 When DDR = 1 and A23E to A20E = 1: Address output When DDR = 1 and A23E to A20E = 0: DR value output Port 2 * 8-bit I/O port * Schmitttriggered input P27/TIOCB5/TMO1 P26/TIOCA5/TMO0 P25/TIOCB4/TMCI1 P24/TIOCA4/TMRI1 P23/TIOCD3/TMCI0 P22/TIOCC3/TMRI0 P21/TIOCB3 P20/TIOCA3 P35/SCK1/IRQ5 P34/SCK0/IRQ4 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 8-bit I/O port also functioning as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5), and 8-bit timer (channels 0 and 1) I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, TMO1)
Port 3 * 6-bit I/O port * Open-drain output capability * Schmitttriggered input (IRQ5, IRQ4)
6-bit I/O port also functioning as SCI (channels 0 and 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1) and interrupt input pins (IRQ5, IRQ4)
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Port
Description
Pins P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0
Mode 4
Mode 5
Mode 6*1
Mode 7*1
Port 4 * 8-bit input port
8-bit input port also functioning as A/D converter analog inputs (AN7 to AN0) and D/A converter analog outputs (DA1 and DA0)
Port A * 4-bit I/O port PA3/A19 to PA0/A16 * Built-in MOS input pull-up * Open-drain output capability
Address output
When DDR = I/O ports 0 (after reset): input ports When DDR = 1: address output
Port B * 8-bit I/O port * Built-in MOS input pull-up
PB7/A15 to PB0/A8
Address output
When DDR = I/O port 0 (after reset): input port When DDR = 1: address output
Port C * 8-bit I/O port * Built-in MOS input pull-up
PC7/A7 to PC0/A0
Address output
When DDR = I/O port 0 (after reset): input port When DDR = 1: address output
Port D * 8-bit I/O port * Built-in MOS input pull-up
PD7/D15 to PD0/D8
Data bus input/output
I/O port
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Port
Description
Pins PE7/D7 to PE0/D0
Mode 4
Mode 5
Mode 6*1
Mode 7*1 I/O port
Port E * 8-bit I/O port * Built-in MOS input pull-up
In 8-bit bus mode: I/O port In 16-bit bus mode: data bus input/output
Port F * 8-bit I/O port PF7/o * Schmitttriggered input (IRQ3 to IRQ0)
When DDR = 0: input port When DDR = 1 (after reset): o output
When DDR = 0 (after reset): input port When DDR = 1: o output
PF6/AS
When ASOD = 1: I/O port When ASOD = 0: AS output
I/O port
PF5/RD PF4/HWR PF3/LWR/IRQ3
RD, HWR output In 8-bit bus mode: When LWROD = 1, I/O I/O port also port functioning as interrupt In 16-bit bus mode: LWR output also input pins functioning as interrupt input pin (IRQ3) (IRQ3 to IRQ0)
PF2/WAIT /IRQ2/BREQO When WAITE = 0, BRLE = 0, BREQOE = 0 (after reset): I/O port also functioning as interrupt input pin (IRQ2) When WAITE = 1: WAIT input also functioning as interrupt input pin (IRQ2) When WAITE = 0, BRLE = 1, BREQOE = 1: BREQO output also functioning as interrupt input pin (IRQ2) PF1/BACK /IRQ1/CS5 PF0/BREQ/IRQ0/CS4 When BRLE = 0 (after reset): I/O port also functioning as interrupt input pins (IRQ1, IRQ0) When CS25E = 1, PF1CS5S = 1, and DDR = 1: Also functions as CS5 output When CS25E = 1, PF0CS4S = 1, and DDR = 1: Also functions as CS4 output When BRLE = 1: BREQ input, BACK output also functioning as interrupt input pins (IRQ1, IRQ0)
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Port
Description PG4/CS0
Pins
Mode 4
Mode 5
Mode 6*1
Mode 7*1 I/O port also functions as interrupt input pins (IRQ7, IRQ6) and A/D converter input pin (ADTRG)
Port G * 5-bit I/O port * Schmitttriggered input (IRQ7, IRQ6)
When DDR = 0*2: input port When DDR = 1*3: CS0 output
PG3/CS1/CS7
I/O port When DDR = 1, CS167E = 1, and CSS17 = 0: Also functions as CS1 output When DDR = 1, CS167E = 1, and CSS17 = 1: Also functions as CS7 output
PG2/CS2
I/O port When DDR = 1 and CS25E = 1: Also functions as CS2 output
PG1/CS3/ IRQ7/CS6
I/O port When DDR = 1, CS25E = 1, and CSS36 = 0: Also functions as CS3 output When DDR = 1, CSS36 = 1, and CS167E = 1: Also functions as CS6 output and interrupt input pin (IRQ7)
PG0/IRQ6/ ADTRG
I/O port also functioning as interrupt input pin (IRQ6) and A/D converter input pin (ADTRG)
Notes: 1. Modes 6 and 7 are not available on the ROMless version. 2. After a reset in mode 6 3. After a reset in mode 4 or 5
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5.2
5.2.1
Port 1
Overview
Port 1 is an 8-bit I/O port. Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2) and an address bus output function. Port 1 pin functions change according to the operating mode. The address output or port output function is selected according to the settings of bits A23E to A20E in PFCR1. Port 1 pins have Schmitt-trigger inputs. Figure 5.1 shows the port 1 pin configuration.
Port 1 pins P17 (I/O)/TIOCB2 (I/O)/TCLKD (input) P16 (I/O)/TIOCA2 (I/O) P15 (I/O)/TIOCB1 (I/O)/TCLKC (input) Port 1 P14 (I/O)/TIOCA1 (I/O) P13 (I/O)/TIOCD0 (I/O)/TCLKB (input)/A23 (output) P12 (I/O)/TIOCC0 (I/O)/TCLKA (input)/A22 (output) P11 (I/O)/TIOCB0 (I/O)/A21 (output) P10 (I/O)/TIOCA0 (I/O)/A20 (output) Pin functions in modes 4 to 6* P17 (I/O)/TIOCB2 (I/O)/TCLKD (input) P16 (I/O)/TIOCA2 (I/O) P15 (I/O)/TIOCB1 (I/O)/TCLKC (input) P14 (I/O)/TIOCA1 (I/O) P13 (I/O)/TIOCD0 (I/O)/TCLKB (input)/A23 (output) P12 (I/O)/TIOCC0 (I/O)/TCLKA (input)/A22 (output) P11 (I/O)/TIOCB0 (I/O)/A21 (output) P10 (I/O)/TIOCA0 (I/O)/A20 (output) Pin functions in mode 7* P17 (I/O)/TIOCB2 (I/O)/TCLKD (input) P16 (I/O)/TIOCA2 (I/O) P15 (I/O)/TIOCB1 (I/O)/TCLKC (input) P14 (I/O)/TIOCA1 (I/O) P13 (I/O)/TIOCD0 (I/O)/TCLKB (input) P12 (I/O)/TIOCC0 (I/O)/TCLKA (input) P11 (I/O)/TIOCB0 (I/O) P10 (I/O)/TIOCA0 (I/O)
Note: * Modes 6 and 7 are not available on the ROMless version.
Figure 5.1 Port 1 Pin Functions
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5.2.2
Register Configuration
Table 5.2 shows the port 1 register configuration. Table 5.2
Name Port 1 data direction register Port 1 data register Port 1 register Port function control register 1
Port 1 Registers
Abbreviation P1DDR P1DR PORT1 PFCR1 R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'0F Address* H'FEB0 H'FF60 H'FF50 H'FF45
Note: * Lower 16 bits of the address.
Port 1 Data Direction Register (P1DDR)
Bit : 7 6 5 4 3 2 1 0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P1DDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state after in software standby mode. Whether the address output pins maintain their output state or go to the high-impedance state in a transition to software standby mode is selected by the OPE bit in SBYCR. Port 1 Data Register (P1DR)
Bit : 7 P17DR Initial value : R/W : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10).
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P1DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state after in software standby mode. Port 1 Register (PORT1)
Bit : 7 P17 Initial value : R/W : --* R 6 P16 --* R 5 P15 --* R 4 P14 --* R 3 P13 --* R 2 P12 --* R 1 P11 --* R 0 P10 --* R
Note: * Determined by state of pins P17 to P10.
PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR. If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORT1 contents are determined by the pin states, as P1DDR and P1DR are initialized. PORT1 retains its prior state after in software standby mode. Port Function Control Register 1 (PFCR1)
Bit : 7 CSS17 Initial value : R/W : 0 R/W 6 5 4 3 A23E 1 R/W 2 A22E 1 R/W 1 A21E 1 R/W 0 A20E 1 R/W
CSS36 PF1CS5S PF0CS4S 0 R/W 0 R/W 0 R/W
PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to H'0F by a reset, and in hardware standby mode. Bit 7--CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin. For details see section 5.12 port G. Bit 6--CS36 Select (CSS36): Selects whether CS3 or CS6 is output from the PG1 pin. For details, see section 5.12 port G. Bit 5--Port F1 Chip Select 5 Select (PF1CS5S): Selects enabling or disabling of CS5 output. For details, see section 5.11 port F. Bit 4--Port F0 Chip Select 4 Select (PF0CS4S): Selects enabling or disabling of CS4 output. For details, see section 5.11 port F.
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Bit 3--Address 23 Enable (A23E): Enables or disables address output 23 (A23). This bit is valid in modes 4 to 6.
Bit 3 A23E 0 1 Description P13DR is output when P13DDR = 1 A23 is output when P13DDR = 1 (Initial value)
Bit 2--Address 22 Enable (A22E): Enables or disables address output 22 (A22). This bit is valid in modes 4 to 6.
Bit 2 A22E 0 1 Description P12DR is output when P12DDR = 1 A22 is output when P12DDR = 1 (Initial value)
Bit 1--Address 21 Enable (A21E): Enables or disables address output 21 (A21). This bit is valid in modes 4 to 6.
Bit 1 A21E 0 1 Description P11DR is output when P11DDR = 1 A21 is output when P11DDR = 1 (Initial value)
Bit 0--Address 20 Enable (A20E): Enables or disables address output 20 (A20). This bit is valid in modes 4 to 6.
Bit 0 A20E 0 1 Description P10DR is output when P10DDR = 1 A20 is output when P10DDR = 1 (Initial value)
5.2.3
Pin Functions
Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2) and address output pins (A23 to A20). Port 1 pin functions are shown in table 5.3.
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Table 5.3
Pin P17/TIOCB2/ TCLKD
Port 1 Pin Functions
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, bits TPSC2 to TPSC0 in TCR0 and TCR5, and bit P17DDR. TPU Channel 2 Setting P17DDR Pin function Table Below (1) -- TIOCB2 output Table Below (2) 0 P17 input TCLKD input * TPU Channel 2 Setting MD3 to MD0 IOB3 to IOB0
2
1 P17 output
TIOCB2 input * 1
(2) B'0000 B'0100 B'1xxx -- --
(1) B'0001 to B'0011 B'0101 to B'0111 -- Output compare output
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
B'0000, B'01xx
Other than B'xx00
CCLR1, CCLR0 Output function
-- --
-- --
Other than B'10 PWM mode 2 output
B'10 --
x: Don't care Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1. 2. TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode (MD3 to MD0 = B'01xx).
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Pin P16/TIOCA2
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, and bit P16DDR. TPU Channel 2 Setting P16DDR Pin function Table Below (1) -- TIOCA2 output Table Below (2) 0 P16 input 1 P16 output
TIOCA2 input * 1
TPU Channel 2 Setting MD3 to MD0 IOA3 to IOA0
(2) B'0000 B'0100 B'1xxx -- --
(1)
(2) B'001x
(1) B'0011
(1) B'0011
(2)
B'0000, B'01xx
B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- Output compare output -- -- --
Other than B'xx00
CCLR1, CCLR0 Output function
Other than B'01 PWM mode 2 output
B'01 --
PWM mode 1 output * 2
x: Don't care Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. 2. TIOCB2 output is disabled.
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Pin P15/TIOCB1/ TCLKC
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, and bit P15DDR. TPU Channel 1 Setting P15DDR Pin function Table Below (1) -- TIOCB1 output Table Below (2) 0 P15 input 1 P15 output
TIOCB1 input * 1 TCLKC input * 2
TPU Channel 1 Setting MD3 to MD0 IOB3 to IOB0
(2) B'0000 B'0100 B'1xxx --
(1) B'0001 to B'0011 B'0101 to B'0111 --
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
B'0000, B'01xx
Other than B'xx00
CCLR1, CCLR0 Output function
--
--
Other than B'10 PWM mode 2 output
B'10
--
Output compare output
--
--
--
x: Don't care Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx. 2. TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2 to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 = B'101. TCLKC input when channels 2 and 4 are set to phase counting mode (MD3 to MD0 = B'01xx).
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Pin P14/TIOCA1
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, and bit P14DDR. TPU Channel 1 Setting P14DDR Pin function Table Below (1) -- TIOCA1 output Table Below (2) 0 P14 input 1 P14 output
TIOCA1 input * 1
TPU Channel 1 Setting MD3 to MD0 IOA3 to IOA0
(2) B'0000 B'0100 B'1xxx -- --
(1)
(2) B'001x
(1) B'0010
(1) B'0011
(2)
B'0000, B'01xx
B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- Output compare output -- -- --
Other than B'xx00
CCLR1, CCLR0 Output function
Other than B'01 PWM mode 2 output
B'01 --
PWM mode 1 output* 2
x: Don't care Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx. 2. TIOCB1 output is disabled.
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Pin P13/TIOCD0/ TCLKB/A23
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit A23E in PFCR1, and bit P13DDR. Operating Mode TPU Channel 0 Setting P13DDR A23E Pin function Mode 7* 1
Table Below (1) Table Below (2) Table Below (1)
Modes 4, 5, 6* 1
Table Below (2)
-- --
TIOCD0 output
0 --
P13
1 --
P13
0 --
output
1 0
output
0 1
A23 output
1 0
P13 output
--
P13 input
1
A23 output
TIOCD0 TIOCD0
input output
TIOCD0 input*2
TIOCD0 input*2
TCLKB input* 3
TPU Channel 0 Setting MD3 to MD0 IOD3 to IOD0
(2) B'0000 B'0000 B'0100 B'1xxx --
(1) B'0001 to B'0011 B'0101 to B'0111 --
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
Other than B'xx00
CCLR2 to CCLR0 Output function
--
--
Other than B'110 PWM mode 2 output
B'110
--
Output compare output
--
--
--
x: Don't care Notes: 1. Modes 6 and 7 are not available on the ROMless version. 2. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx. 3. TCLKB input when the TCR0, TCR1, or TCR2 setting is: TPSC2 to TPSC0 = B'101. TCLKB input when channels 1 and 5 are set to phase counting mode (MD3 to MD0 = B'01xx).
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Pin P12/TIOCC0/ TCLKA/A22
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit A22E in PFCR1 and bit P12DDR. Operating Mode TPU Channel 0 Setting P12DDR A22E Pin function Mode 7* 1
Table Below (1) Table Below (2) Table Below (1)
Modes 4, 5, 6* 1
Table Below (2)
-- --
TIOCC0 output
0 --
P12
1 --
P12
0 --
output
1 0
output
0 1
A22 output
1 0
P12 output
--
P12 input
1
A22 output
TIOCC0 TIOCC0
input output
TIOCC0 input*2
TIOCC0 input*2
TCLKA input* 3
TPU Channel 0 Setting MD3 to MD0 IOC3 to IOC0
(2) B'0000 B'0000 B'0100 B'1xxx --
(1) B'0001 to B'0011 B'0101 to B'0111 --
(2) B'001x B'xx00
(1) B'0010
(1) B'0011 Other than B'xx00
(2)
CCLR2 to CCLR0 Output function
--
--
Other than B'101 PWM mode 2 output
B'101
--
Output compare output
--
PWM mode 1 output* 4
--
x: Don't care Notes: 1. Modes 6 and 7 are not available on the ROMless version. 2. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. 3. TCLKA input when the TCR0 to TCR5 setting is: TPSC2 to TPSC0 = B'100. TCLKA input when channel 1 and 5 are set to phase counting mode (MD3 to MD0 = B'01xx). 4. TIOCD0 output is disabled. When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting (2) applies.
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Pin P11/TIOCB0/ A21
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOB3 to IOB0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit A21E in PFCR1 and bit P11DDR. Operating Mode TPU Channel 0 Setting P11DDR A21E Pin function Mode 7* 1
Table Below (1) Table Below (2) Table Below (1)
Modes 4, 5, 6* 1
Table Below (2)
-- --
TIOCB0 output
0 --
P11
1 --
P11
0 --
output
1 0
output
0 1
A21 output
1 0
P11 output
--
P11 input
1
A21 output
TIOCB0 TIOCB0
input output
TIOCB0 input*2
TIOCB0 input*2
TCLKB input* 3
TPU Channel 0 Setting MD3 to MD0 IOB3 to IOB0
(2) B'0000 B'0000 B'0100 B'1xxx --
(1) B'0001 to B'0011 B'0101 to B'0111 --
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
Other than B'xx00
CCLR2 to CCLR0 Output function
--
--
Other than B'010 PWM mode 2 output
B'010
--
Output compare output
--
--
--
x: Don't care Notes: 1. Modes 6 and 7 are not available on the ROMless version. 2. TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
108
Pin P10/TIOCA0/ A20
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit A20E in PFCR1 and bit P10DDR. Operating Mode TPU Channel 0 Setting P10DDR A20E Pin function Mode 7* 1
Table Below (1) Table Below (2) Table Below (1)
Modes 4, 5, 6* 1
Table Below (2)
-- --
TIOCA0 output
0 --
P10
1 --
P10
0 --
output
1 0
output
0 1
A20 output
1 0
P10 output
--
P10 input
1
A20 output
TIOCA0 TIOCA0
input output
TIOCA0 input*2
TIOCA0 input*2
TPU Channel 0 Setting MD3 to MD0 IOA3 to IOA0
(2) B'0000 B'0000 B'0100 B'1xxx --
(1) B'0001 to B'0011 B'0101 to B'0111 --
(2) B'001x B'xx00
(1) B'0010
(1) B'0011
(2)
Other than B'xx00
CCLR2 to CCLR0 Output function
--
--
Other than B'001 PWM mode 2 output
B'001
--
Output compare output
--
PWM mode 1 output* 3
--
x: Don't care Notes: 1. Modes 6 and 7 are not available on the ROMless version. 2. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx. 3. TIOCB0 output is disabled.
109
5.3
5.3.1
Port 2
Overview
Port 2 is an 8-bit I/O port. Port 2 pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are the same in all operating modes. Port 2 uses Schmitt-triggered input. Figure 5.2 shows the port 2 pin configuration.
Port 2 pins P27 (I/O)/TIOCB5 (I/O)/TMO1 (output) P26 (I/O)/TIOCA5 (I/O)/TMO0 (output) P25 (I/O)/TIOCB4 (I/O)/TMCI1 (input) Port 2 P24 (I/O)/TIOCA4 (I/O)/TMRI1 (input) P23 (I/O)/TIOCD3 (I/O)/TMCI0 (input) P22 (I/O)/TIOCC3 (I/O)/TMRI0 (input) P21 (I/O)/TIOCB3 (I/O) P20 (I/O)/TIOCA3 (I/O)
Figure 5.2 Port 2 Pin Functions 5.3.2 Register Configuration
Table 5.4 shows the port 2 register configuration. Table 5.4
Name Port 2 data direction register Port 2 data register Port 2 register
Port 2 Registers
Abbreviation P2DDR P2DR PORT2 R/W W R/W R Initial Value H'00 H'00 Undefined Address* H'FEB1 H'FF61 H'FF51
Note: * Lower 16 bits of the address.
110
Port 2 Data Direction Register (P2DDR)
Bit : 7 6 5 4 3 2 1 0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read. Setting a P2DDR bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P2DDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state after in software standby mode. Port 2 Data Register (P2DR)
Bit : 7 P27DR Initial value : R/W : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W
P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20). P2DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state after in software standby mode. Port 2 Register (PORT2)
Bit : 7 P27 Initial value : R/W : --* R 6 P26 --* R 5 P25 --* R 4 P24 --* R 3 P23 --* R 2 P22 --* R 1 P21 --* R 0 P20 --* R
Note: * Determined by state of pins P27 to P20.
PORT2 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 2 pins (P27 to P20) must always be performed on P2DR. If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read.
111
After a reset and in hardware standby mode, PORT2 contents are determined by the pin states, as P2DDR and P2DR are initialized. PORT2 retains its prior state after in software standby mode. 5.3.3 Pin Functions
Port 2 pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are shown in table 5.5. Table 5.5
Pin P27/TIOCB5/ TMO1
Port 2 Pin Functions
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOB3 to IOB0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bits OS3 to OS0 in TCSR1, and bit P27DDR. OS3 to OS0 TPU Channel 5 Setting P27DDR Pin function Table Below (1) -- TIOCB5 output All 0 Table Below (2) 0 P27 input 1 P27 output TIOCB5 input * Any 1 -- -- TMO1 output
TPU Channel 5 Setting MD3 to MD0 IOB3 to IOB0
(2) B'0000 B'0100 B'1xxx -- --
(1) B'0001 to B'0011 B'0101 to B'0111 -- Output compare output
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
B'0000, B'01xx
Other than B'xx00
CCLR1, CCLR0 Output function
-- --
-- --
Other than B'10 PWM mode 2 output
B'10 --
x: Don't care Note: * TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.
112
Pin P26/TIOCA5/ TMO0
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bits OS3 to OS0 in TCSR0, and bit P26DDR. OS3 to OS0 TPU Channel 5 Setting P26DDR Pin function Table Below (1) -- TIOCA5 output All 0 Table Below (2) 0 P26 input 1 P26 output TIOCA5 input * 1 Any 1 -- -- TMO0 output
TPU Channel 5 Setting MD3 to MD0 IOA3 to IOA0
(2) B'0000 B'0100 B'1xxx -- --
(1)
(2) B'001x
(1) B'0010
(1) B'0011
(2)
B'0000, B'01xx
B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- Output compare output -- -- --
Other than B'xx00
CCLR1, CCLR0 Output function
Other than B'01 PWM mode 2 output
B'01 --
PWM mode 1 output* 2
x: Don't care Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1. 2. TIOCB5 output is disabled.
113
Pin P25/TIOCB4/ TMCI1
Selection Method and Pin Functions This pin is used as the 8-bit timer external clock input pin when external clock is selected with bits CKS2 to CKS0 in TCR1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4 and bits IOB3 to IOB0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, and bit P25DDR. TPU Channel 4 Setting P25DDR Pin function Table Below (1) -- TIOCB4 output Table Below (2) 0 P25 input 1 P25 output
TIOCB4 input * TMCI1 input
TPU Channel 4 Setting MD3 to MD0 IOB3 to IOB0
(2) B'0000 B'0100 B'1xxx -- --
(1) B'0001 to B'0011 B'0101 to B'0111 -- Output compare output
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
B'0000, B'01xx
Other than B'xx00
CCLR1, CCLR0 Output function
-- --
-- --
Other than B'10 PWM mode 2 output
B'10 --
x: Don't care Note: * TIOCB4 input when MD3 to MD0 = B'0000 or B'10xx and IOB3 to IOB0 = B'10xx.
114
Pin P24/TIOCA4/ TMRI1
Selection Method and Pin Functions This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR1 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, and bit P24DDR. TPU Channel 4 Setting P24DDR Pin function Table Below (1) -- TIOCA4 output Table Below (2) 0 P24 input 1 P24 output
TIOCA4 input * 1 TMRI1 input
TPU Channel 4 Setting MD3 to MD0 IOA3 to IOA0
(2) B'0000 B'0100 B'1xxx -- --
(1)
(2) B'001x
(1) B'0010
(1) B'0011
(2)
B'0000, B'01xx
B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- Output compare output -- -- --
Other than B'xx00
CCLR1, CCLR0 Output function
Other than B'01 PWM mode 2 output
B'01 --
PWM mode 1 output* 2
x: Don't care Notes: 1. TIOCA4 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx. 2. TIOCB4 output is disabled.
115
Pin P23/TIOCD3/ TMCI0
Selection Method and Pin Functions This pin is used as the 8-bit timer external clock input pin when external clock is selected with bits CKS2 to CKS0 in TCR0. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, and bit P23DDR. TPU Channel 3 Setting P23DDR Pin function Table Below (1) -- TIOCD3 output Table Below (2) 0 P23 input 1 P23 output
TIOCD3 input * TMCI0 input
TPU Channel 3 Setting MD3 to MD0 IOD3 to IOD0
(2) B'0000 B'0000 B'0100 B'1xxx --
(1) B'0001 to B'0011 B'0101 to B'0111 --
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
Other than B'xx00
CCLR2 to CCLR0 Output function
--
--
Other than B'110 PWM mode 2 output
B'110
--
Output compare output
--
--
--
x: Don't care Note: * TIOCD3 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.
116
Pin P22/TIOCC3/ TMRI0
Selection Method and Pin Functions This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR0 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, and bit P22DDR. TPU Channel 3 Setting P22DDR Pin function Table Below (1) -- TIOCC3 output Table Below (2) 0 P22 input 1 P22 output
TIOCC3 input * 1 TMRI0 input
TPU Channel 3 Setting MD3 to MD0 IOC3 to IOC0
(2) B'0000 B'0000 B'0100 B'1xxx --
(1)
(2) B'001x
(1) B'0010
(1) B'0011
(2)
B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- -- --
Other than B'xx00
CCLR2 to CCLR0 Output function
Other than B'101 PWM mode 2 output
B'101
--
Output compare output
--
PWM mode 1 output* 2
--
x: Don't care Notes: 1. TIOCC3 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx. 2. TIOCD3 output is disabled. When BFA = 1 or BFB = 1 in TMDR3, output is disabled and setting (2) applies.
117
Pin P21/TIOCB3
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, and bit P21DDR. TPU Channel 3 Setting P21DDR Pin function Table Below (1) -- TIOCB3 output Table Below (2) 0 P21 input 1 P21 output
TIOCB3 input *
TPU Channel 3 Setting MD3 to MD0 IOB3 to IOB0
(2) B'0000 B'0000 B'0100 B'1xxx --
(1) B'0001 to B'0011 B'0101 to B'0111 --
(2) B'0010 --
(2) B'xx00
(1) B'0011
(2)
Other than B'xx00
CCLR2 to CCLR0 Output function
--
--
Other than B'010 PWM mode 2 output
B'010
--
Output compare output
--
--
--
x: Don't care Note: * TIOCB3 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
118
Pin P20/TIOCA3
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, and bit P20DDR. TPU Channel 3 Setting P20DDR Pin function Table Below (1) -- TIOCA3 output Table Below (2) 0 P20 input 1 P20 output
TIOCA3 input * 1
TPU Channel 3 Setting MD3 to MD0 IOA3 to IOA0
(2) B'0000 B'0000 B'0100 B'1xxx --
(1)
(2) B'001x
(1) B'0010
(1) B'0011
(2)
B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- -- --
Other than B'xx00
CCLR2 to CCLR0 Output function
Other than B'001 PWM mode 2 output
B'001
--
Output compare output
--
PWM mode 1 output* 2
--
x: Don't care Notes: 1. TIOCA3 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx. 2. TIOCB3 output is disabled.
119
5.4
5.4.1
Port 3
Overview
Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and interrupt input pins (IRQ4, IRQ5). Port 3 pin functions are the same in all operating modes. The interrupt input pins (IRQ4, IRQ5) are Schmitt-triggered inputs. Figure 5.3 shows the port 3 pin configuration.
Port 3 pins
P35 (I/O)/ SCK1(I/O)/ IRQ5 (input) P34 (I/O)/ SCK0(I/O)/ IRQ4 (input) Port 3 P33 (I/O)/ RxD1 (input) P32 (I/O)/ RxD0 (input) P31 (I/O)/ TxD1 (output) P30 (I/O)/ TxD0 (output)
Figure 5.3 Port 3 Pin Functions 5.4.2 Register Configuration
Table 5.6 shows the port 3 register configuration. Table 5.6
Name Port 3 data direction register Port 3 data register Port 3 register Port 3 open drain control register
Port 3 Registers
Abbreviation P3DDR P3DR PORT3 P3ODR R/W W R/W R R/W Initial Value* 1 H'00 H'00 Undefined H'00 Address* 2 H'FEB2 H'FF62 H'FF52 H'FF76
Notes: 1. Value of bits 5 to 0. 2. Lower 16 bits of the address.
120
Port 3 Data Direction Register (P3DDR)
Bit : 7 -- 6 -- 5 4 3 2 1 0
P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR 0 W 0 W 0 W 0 W 0 W 0 W
Initial value : Undefined Undefined R/W : -- --
P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. Bits 7 and 6 are reserved. P3DDR cannot be read; if it is, an undefined value will be read. Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P3DDR is initialized to H'00 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its prior state after in software standby mode. As the SCI is initialized, the pin states are determined by the P3DDR and P3DR specifications. Port 3 Data Register (P3DR)
Bit : 7 -- 6 -- 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W
Initial value : Undefined Undefined R/W : -- --
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P35 to P30). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. P3DR is initialized to H'00 (bits 5 to 0) by a on reset, and in hardware standby mode. It retains its prior state after in software standby mode.
121
Port 3 Register (PORT3)
Bit : 7 -- 6 -- 5 P35 --* R 4 P34 --* R 3 P33 --* R 2 P32 --* R 1 P31 --* R 0 P30 --* R
Initial value : Undefined Undefined R/W : -- --
Note: * Determined by state of pins P35 to P30.
PORT3 is an 8-bit read-only register that shows the pin states, and cannot be modified. Writing of output data for the port 3 pins (P35 to P30) must always be performed on P3DR. Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORT3 contents are determined by the pin states, as P3DDR and P3DR are initialized. PORT3 retains its prior state after in software standby mode. Port 3 Open Drain Control Register (P3ODR)
Bit : 7 -- 6 -- 5 4 3 2 1 0
P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
Initial value : Undefined Undefined R/W : -- --
P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3 pin (P35 to P30). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin. P3ODR is initialized to H'00 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its prior state after in software standby mode.
122
5.4.3
Pin Functions
Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and interrupt input pins (IRQ4, IRQ5). Port 3 pin functions are shown in table 5.7. Table 5.7
Pin P35/SCK1/IRQ5
Port 3 Pin Functions
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit C/A in the SCI1 SMR, bits CKE0 and CKE1 in SCR, and bit P35DDR. CKE1 C/A CKE0 P35DDR Pin function 0 0 1 0 1 -- 0 1 -- -- 1 -- -- -- SCK1 input pin
P35 P35 SCK1 SCK1 input pin output pin* 1 output pin* 1 output pin* 1 IRQ5 interrupt input pin* 2
Notes: 1. When P35ODR = 1, the pin becomes an NMOS open-drain output. 2. When this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. P34/SCK0/IRQ4 The pin function is switched as shown below according to the combination of bit C/A in the SCI0 SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR. CKE1 C/A CKE0 P34DDR Pin function 0 0 1 0 1 -- 0 1 -- -- 1 -- -- -- SCK0 input pin
P34 P34 SCK0 SCK0 input pin output pin* 1 output pin* 1 output pin* 1 IRQ4 interrupt input pin* 2
Notes: 1. When P34ODR = 1, the pin becomes an NMOS open-drain output. 2. When this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions.
123
Pin P33/RxD1
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit RE in the SCI1 SCR, and bit P33DDR. RE P33DDR Pin function 0 P33 input pin 0 1 P33 output pin* 1 -- RxD1 input pin
Note: * When P33ODR = 1, the pin becomes an NMOS open-drain output. P32/RxD0 The pin function is switched as shown below according to the combination of bit RE in the SCI0 SCR, and bit P32DDR. RE P32DDR Pin function 0 P32 input pin 0 1 P32 output pin* 1 -- RxD0 input pin
Note: * When P32ODR = 1, the pin becomes an NMOS open-drain output. P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in the SCI1 SCR, and bit P31DDR. TE P31DDR Pin function 0 P31 input pin 0 1 P31 output pin* 1 -- TxD1 output pin
Note: * When P31ODR = 1, the pin becomes an NMOS open-drain output. P30/TxD0 The pin function is switched as shown below according to the combination of bit TE in the SCI0 SCR, and bit P30DDR. TE P30DDR Pin function 0 P30 input pin 0 1 P30 output pin* 1 -- TxD0 output pin
Note: * When P30ODR = 1, the pin becomes an NMOS open-drain output.
124
5.5
5.5.1
Port 4
Overview
Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the same in all operating modes. Figure 5.4 shows the port 4 pin configuration.
Port 4 pins P47 (input) / AN7 (input) / DA1 (output) P46 (input) / AN6 (input) / DA0 (output) P45 (input) / AN5 (input) Port 4 P44 (input) / AN4 (input) P43 (input) / AN3 (input) P42 (input) / AN2 (input) P41 (input) / AN1 (input) P40 (input) / AN0 (input)
Figure 5.4 Port 4 Pin Functions 5.5.2 Register Configuration
Table 5.8 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 5.8
Name Port 4 register
Port 4 Register
Abbreviation PORT4 R/W R Initial Value Undefined Address* H'FF53
Note: * Lower 16 bits of the address.
Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed.
Bit : 7 P47 Initial value : R/W : --* R 6 P46 --* R 5 P45 --* R 4 P44 --* R 3 P43 --* R 2 P42 --* R 1 P41 --* R 0 P40 --* R
Note: * Determined by state of pins P47 to P40. 125
5.5.3
Pin Functions
Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1).
5.6
5.6.1
Port A
Overview
Port A is a 4-bit I/O port. Port A pins also function as address bus outputs. The pin functions change according to the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software. Figure 5.5 shows the port A pin configuration.
Port A pins PA3/ A19 PA2/ A18 Port A PA1/ A17 PA0/ A16 Pin functions in modes 4 and 5 A19 (output) A18 (output) A17 (output) A16 (output)
Pin functions in mode 6* PA3 (input)/A19 (output) PA2 (input)/A18 (output) PA1 (input)/A17 (output) PA0 (input)/A16 (output)
Pin functions in mode 7* PA3 (I/O) PA2 (I/O) PA1 (I/O) PA0 (I/O)
Note: * Modes 6 and 7 are not available on the ROMless version.
Figure 5.5 Port A Pin Functions
126
5.6.2
Register Configuration
Table 5.9 shows the port A register configuration. Table 5.9
Name Port A data direction register Port A data register Port A register Port A MOS pull-up control register Port A open-drain control register
Port A Registers
Abbreviation PADDR PADR PORTA PAPCR PAODR R/W W R/W R R/W R/W Initial Value* 1 H'0 H'0 Undefined H'0 H'0 Address* 2 H'FEB9 H'FF69 H'FF59 H'FF70 H'FF77
Notes: 1. Value of bits 3 to 0. 2. Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
Bit 7 -- Initial value R/W 6 -- 5 -- 4 -- 3 2 1 0
PA3DDR PA2DDR PA1DDR PA0DDR 0 W 0 W 0 W 0 W
Undefined Undefined Undefined Undefined -- -- -- --
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bits 7 to 4 are reserved. PADDR is initialized to H'0 (bits 3 to 0) by a reset and in hardware standby mode. It retains its prior state after in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 and 5 The corresponding port A pins are address outputs irrespective of the value of bits PA3DDR to PA0DDR. * Mode 6* Setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing the bit to 0 makes the pin an input port.
127
* Mode 7* Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Note: * Modes 6 and 7 are not available on the ROMless version. Port A Data Register (PADR)
Bit : 7 -- 6 -- 5 -- 4 -- 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W
Initial value : Undefined Undefined Undefined Undefined R/W : -- -- -- --
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA3 to PA0). Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. PADR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its prior state after in software standby mode. Port A Register (PORTA)
Bit : 7 -- 6 -- 5 -- 4 -- 3 PA3 --* R 2 PA2 --* R 1 PA1 --* R 0 PA0 --* R
Initial value : Undefined Undefined Undefined Undefined R/W : -- -- -- -- Note: * Determined by state of pins PA3 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port A pins (PA3 to PA0) must always be performed on PADR. Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and PADR are initialized. PORTA retains its prior state after in software standby mode.
128
Port A MOS Pull-Up Control Register (PAPCR)
Bit : 7 -- 6 -- 5 -- 4 -- 3 2 1 0
PA3PCR PA2PCR PA1PCR PA0PCR 0 R/W 0 R/W 0 R/W 0 R/W
Initial value : Undefined Undefined Undefined Undefined R/W : -- -- -- --
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. Bits 3 to 0 are valid in modes 6 and 7*, and all the bits are invalid in modes 4 and 5. When a PADDR bit is cleared to 0 (input port setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PAPCR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its prior state after in software standby mode. Note: * Modes 6 and 7 are not available on the ROMless version. Port A Open Drain Control Register (PAODR)
Bit : 7 -- 6 -- 5 -- 4 -- 3 2 1 0
PA3ODR PA2ODR PA1ODR PA0ODR 0 R/W 0 R/W 0 R/W 0 R/W
Initial value : Undefined Undefined Undefined Undefined R/W : -- -- -- --
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA3 to PA0). Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. All bits are valid in mode 7.* Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. PAODR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its prior state after in software standby mode. Note: * Modes 6 and 7 are not available on the ROMless version.
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5.6.3
Pin Functions
Modes 4 and 5: In modes 4 and 5, the lower 4 bits of port A are designated as address outputs automatically. Port A pin functions in modes 4 and 5 are shown in figure 5.6.
A19 (output) A18 (output) Port A A17 (output) A16 (output)
Figure 5.6 Port A Pin Functions (Modes 4 and 5) Mode 6*: In mode 6*, port A pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port. Port A pin functions in mode 6 are shown in figure 5.7.
When PADDR = 1 A19 (output) A18 (output) Port A A17 (output) A16 (output) PA1 (input) PA0 (input) When PADDR = 0 PA3 (input) PA2 (input)
Figure 5.7 Port A Pin Functions (Mode 6) Mode 7*: In mode 7*, port A pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Port A pin functions in mode 7 are shown in figure 5.8.
130
PA3 (I/O) PA2 (I/O) Port A PA1 (I/O) PA0 (I/O)
Figure 5.8 Port A Pin Functions (Mode 7) Note: * Modes 6 and 7 are not available on the ROMless version. 5.6.4 MOS Input Pull-Up Function
Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7*, and cannot be used in modes 4 and 5. MOS input pull-up can be specified as on or off on an individual bit basis. When a PADDR bit is cleared to 0, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained after in software standby mode. Table 5.10 summarizes the MOS input pull-up states. Table 5.10 MOS Input Pull-Up States (Port A)
Modes 6, 7* 4, 5 Reset PA3 to PA0 OFF PA3 to PA0 Hardware Standby Software Standby Mode Mode OFF ON/OFF OFF In Other Operations ON/OFF OFF
Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PADDR = 0 and PAPCR = 1; otherwise off. Note: * Modes 6 and 7 are not available on the ROMless version.
131
5.7
5.7.1
Port B
Overview
Port B is an 8-bit I/O port. Port B has an address bus output function, and the pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 5.9 shows the port B pin configuration.
Port B pins PB7 / A15 PB6 / A14 PB5 / A13 PB4 / A12 Port B PB3 / A11 PB2 / A10 PB1 / A9 PB0 / A8 Pin functions in modes 4 and 5 A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output)
Pin functions in mode 6* PB7 (input) / A15 (output) PB6 (input) / A14 (output) PB5 (input) / A13 (output) PB4 (input) / A12 (output) PB3 (input) / A11 (output) PB2 (input) / A10 (output) PB1 (input) / A9 (output) PB0 (input) / A8 (output)
Pin functions in mode 7* PB7 (I/O) PB6 (I/O) PB5 (I/O) PB4 (I/O) PB3 (I/O) PB2 (I/O) PB1 (I/O) PB0 (I/O)
Note: * Modes 6 and 7 are not available on the ROMless version.
Figure 5.9 Port B Pin Functions
132
5.7.2
Register Configuration
Table 5.11 shows the port B register configuration. Table 5.11 Port B Registers
Name Port B data direction register Port B data register Port B register Port B MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PBDDR PBDR PORTB PBPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBA H'FF6A H'FF5A H'FF71
Port B Data Direction Register (PBDDR)
Bit : 7 6 5 4 3 2 1 0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 and 5 The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits. * Mode 6* Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port. * Mode 7* Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. Note: * Modes 6 and 7 are not available on the ROMless version.
133
Port B Data Register (PBDR)
Bit : 7 PB7DR Initial value : R/W : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port B Register (PORTB)
Bit : 7 PB7 Initial value : R/W : --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R 3 PB3 --* R 2 PB2 --* R 1 PB1 --* R 0 PB0 --* R
Note: * Determined by state of pins PB7 to PB0.
PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB7 to PB0) must always be performed on PBDR. If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTB contents are determined by the pin states, as PBDDR and PBDR are initialized. PORTB retains its prior state in software standby mode.
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Port B MOS Pull-Up Control Register (PBPCR)
Bit : 7 6 5 4 3 2 1 0
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis. When a PBDDR bit is cleared to 0 (input port setting) in mode 6 or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PBPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. 5.7.3 Pin Functions
Modes 4 and 5: In modes 4 and 5, port B pins are automatically designated as address outputs. Port B pin functions in modes 4 and 5 are shown in figure 5.10.
A15 (output) A14 (output) A13 (output) Port B A12 (output) A11 (output) A10 (output) A9 (output) A8 (output)
Figure 5.10 Port B Pin Functions (Modes 4 and 5)
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Mode 6*: In mode 6, port B pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port. Port B pin functions in mode 6 are shown in figure 5.11
When PBDDR = 1 A15 (output) A14 (output) A13 (output) Port B A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) When PBDDR = 0 PB7 (input) PB6 (input) PB5 (input) PB4 (input) PB3 (input) PB2 (input) PB1 (input) PB0 (input)
Figure 5.11 Port B Pin Functions (Mode 6) Mode 7*: In mode 7, port B pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. Port B pin functions in mode 7 are shown in figure 5.12.
PB7 (I/O) PB6 (I/O) PB5 (I/O) Port B PB4 (I/O) PB3 (I/O) PB2 (I/O) PB1 (I/O) PB0 (I/O)
Figure 5.12 Port B Pin Functions (Mode 7) Note: * Modes 6 and 7 are not available on the ROMless version.
136
5.7.4
MOS Input Pull-Up Function
Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. When a PBDDR bit is cleared to 0 in mode 6 or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 5.12 summarizes the MOS input pull-up states. Table 5.12 MOS Input Pull-Up States (Port B)
Modes 4, 5 6, 7 Reset OFF Hardware Standby Mode OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF
Legend OFF: MOS input pull-up is always off. ON/OFF: On when PBDDR = 0 and PBPCR = 1; otherwise off.
137
5.8
5.8.1
Port C
Overview
Port C is an 8-bit I/O port. Port C has an address bus output function, and the pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 5.13 shows the port C pin configuration.
Port C pins PC7 / A7 PC6 / A6 PC5 / A5 Port C PC4 / A4 PC3 / A3 PC2 / A2 PC1 / A1 PC0 / A0 Pin functions in modes 4 and 5 A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output)
Pin functions in mode 6* PC7 (input) / A7 (output) PC6 (input) / A6 (output) PC5 (input) / A5 (output) PC4 (input) / A4 (output) PC3 (input) / A3 (output) PC2 (input) / A2 (output) PC1 (input) / A1 (output) PC0 (input) / A0 (output)
Pin functions in mode 7* PC7 (I/O) PC6 (I/O) PC5 (I/O) PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O)
Note: * Modes 6 and 7 are not available on the ROMless version.
Figure 5.13 Port C Pin Functions
138
5.8.2
Register Configuration
Table 5.13 shows the port C register configuration. Table 5.13 Port C Registers
Name Port C data direction register Port C data register Port C register Port C MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PCDDR PCDR PORTC PCPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBB H'FF6B H'FF5B H'FF72
Port C Data Direction Register (PCDDR)
Bit : 7 6 5 4 3 2 1 0
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. PCDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 4 and 5 The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits. * Mode 6* Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. * Mode 7* Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. Note: * Modes 6 and 7 are not available on the ROMless version.
139
Port C Data Register (PCDR)
Bit : 7 PC7DR Initial value : R/W : 0 R/W 6 PC6DR 0 R/W 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W
PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port C Register (PORTC)
Bit : 7 PC7 Initial value : R/W : --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R 3 PC3 --* R 2 PC2 --* R 1 PC1 --* R 0 PC0 --* R
Note: * Determined by state of pins PC7 to PC0.
PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC7 to PC0) must always be performed on PCDR. If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTC contents are determined by the pin states, as PCDDR and PCDR are initialized. PORTC retains its prior state in software standby mode.
140
Port C MOS Pull-Up Control Register (PCPCR)
Bit : 7 6 5 4 3 2 1 0
PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis. When a PCDDR bit is cleared to 0 (input port setting) in mode 6 or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PCPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. 5.8.3 Pin Functions
Modes 4 and 5: In modes 4 and 5, port C pins are automatically designated as address outputs. Port C pin functions in modes 4 and 5 are shown in figure 5.14.
A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output)
Figure 5.14 Port C Pin Functions (Modes 4 and 5)
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Mode 6*: In mode 6, port C pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. Port C pin functions in mode 6 are shown in figure 5.15.
When PCDDR = 1 A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) When PCDDR = 0 PC7 (input) PC6 (input) PC5 (input) PC4 (input) PC3 (input) PC2 (input) PC1 (input) PC0 (input)
Figure 5.15 Port C Pin Functions (Mode 6) Mode 7*: In mode 7, port C pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. Port C pin functions in mode 7 are shown in figure 5.16.
PC7 (I/O) PC6 (I/O) PC5 (I/O) Port C PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O)
Figure 5.16 Port C Pin Functions (Mode 7) Note: * Modes 6 and 7 are not available on the ROMless version.
142
5.8.4
MOS Input Pull-Up Function
Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. When a PCDDR bit is cleared to 0 in mode 6 or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 5.14 summarizes the MOS input pull-up states. Table 5.14 MOS Input Pull-Up States (Port C)
Modes 4, 5 6, 7 Reset OFF Hardware Standby Mode OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF
Legend OFF: MOS input pull-up is always off. ON/OFF: On when PCDDR = 0 and PCPCR = 1; otherwise off.
143
5.9
5.9.1
Port D
Overview
Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 5.17 shows the port D pin configuration.
Port D pins PD7 / D15 PD6 / D14 PD5 / D13 Port D PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 Pin functions in modes 4 to 6* D15 (I/O) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) Pin functions in mode 7* PD7 (I/O) PD6 (I/O) PD5 (I/O) PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Note: * Modes 6 and 7 are not available on the ROMless version.
Figure 5.17 Port D Pin Functions
144
5.9.2
Register Configuration
Table 5.15 shows the port D register configuration. Table 5.15 Port D Registers
Name Port D data direction register Port D data register Port D register Port D MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PDDDR PDDR PORTD PDPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBC H'FF6C H'FF5C H'FF73
Port D Data Direction Register (PDDDR)
Bit : 7 6 5 4 3 2 1 0
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read. PDDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. * Modes 4 to 6* The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O. * Mode 7* Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. Note: * Modes 6 and 7 are not available on the ROMless version.
145
Port D Data Register (PDDR)
Bit : 7 PD7DR Initial value : R/W : 0 R/W 6 PD6DR 0 R/W 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port D Register (PORTD)
Bit : 7 PD7 Initial value : R/W : --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R 3 PD3 --* R 2 PD2 --* R 1 PD1 --* R 0 PD0 --* R
Note: * Determined by state of pins PD7 to PD0.
PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD0) must always be performed on PDDR. If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTD contents are determined by the pin states, as PDDDR and PDDR are initialized. PORTD retains its prior state in software standby mode.
146
Port D MOS Pull-Up Control Register (PDPCR)
Bit : 7 6 5 4 3 2 1 0
PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis. When a PDDDR bit is cleared to 0 (input port setting) in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PDPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. 5.9.3 Pin Functions
Modes 4 to 6*: In modes 4 to 6, port D pins are automatically designated as data I/O pins. Port D pin functions in modes 4 to 6 are shown in figure 5.18.
D15 (I/O) D14 (I/O) D13 (I/O) Port D D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O)
Figure 5.18 Port D Pin Functions (Modes 4 to 6)
147
Mode 7*: In mode 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. Port D pin functions in mode 7 are shown in figure 5.19.
PD7 (I/O) PD6 (I/O) PD5 (I/O) Port D PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O)
Figure 5.19 Port D Pin Functions (Mode 7) Note: * Modes 6 and 7 are not available on the ROMless version. 5.9.4 MOS Input Pull-Up Function
Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis. When a PDDDR bit is cleared to 0 in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 5.16 summarizes the MOS input pull-up states.
148
Table 5.16 MOS Input Pull-Up States (Port D)
Modes 4 to 6 7 Reset OFF Hardware Standby Mode OFF Software Standby Mode OFF ON/OFF In Other Operations OFF ON/OFF
Legend OFF: MOS input pull-up is always off. ON/OFF: On when PDDDR = 0 and PDPCR = 1; otherwise off.
149
5.10
5.10.1
Port E
Overview
Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 5.20 shows the port E pin configuration.
Port E pins PE7 / D7 PE6 / D6 PE5 / D5 Port E PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 Pin functions in modes 4 to 6* PE7 (I/O) / D7 (I/O) PE6 (I/O) / D6 (I/O) PE5 (I/O) / D5 (I/O) PE4 (I/O) / D4 (I/O) PE3 (I/O) / D3 (I/O) PE2 (I/O) / D2 (I/O) PE1 (I/O) / D1 (I/O) PE0 (I/O) / D0 (I/O) Pin functions in mode 7* PE7 (I/O) PE6 (I/O) PE5 (I/O) PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Note: * Modes 6 and 7 are not available on the ROMless version.
Figure 5.20 Port E Pin Functions
150
5.10.2
Register Configuration
Table 5.17 shows the port E register configuration. Table 5.17 Port E Registers
Name Port E data direction register Port E data register Port E register Port E MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PEDDR PEDR PORTE PEPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* H'FEBD H'FF6D H'FF5D H'FF74
Port E Data Direction Register (PEDDR)
Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : R/W :
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. PEDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. * Modes 4 to 6* When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. For details of 8-bit and 16-bit bus modes, see section 4, Bus Controller. * Mode 7* Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. Note: * Modes 6 and 7 are not available on the ROMless version.
151
Port E Data Register (PEDR)
Bit : 7 PE7DR Initial value : R/W : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. Port E Register (PORTE)
Bit : 7 PE7 Initial value : R/W : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R 3 PE3 --* R 2 PE2 --* R 1 PE1 --* R 0 PE0 --* R
Note: * Determined by state of pins PE7 to PE0.
PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR. If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed while PEDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTE contents are determined by the pin states, as PEDDR and PEDR are initialized. PORTE retains its prior state in software standby mode.
152
Port E MOS Pull-Up Control Register (PEPCR)
Bit : 7 6 5 4 3 2 1 0
PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W : 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W
PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis. When a PEDDR bit is cleared to 0 (input port setting) in mode 4, 5, or 6 with 8-bit bus mode selected, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PEPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode. 5.10.3 Pin Functions
Modes 4 to 6*: In modes 4 to 6, when 8-bit access is designated and 8-bit bus mode is selected, port E pins are automatically designated as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode is selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. Port E pin functions in modes 4 to 6 are shown in figure 5.21.
8-bit bus mode PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) 16-bit bus mode D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O)
Figure 5.21 Port E Pin Functions (Modes 4 to 6)
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Mode 7*: In mode 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. Port E pin functions in mode 7 are shown in figure 5.22.
PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O)
Figure 5.22 Port E Pin Functions (Mode 7) Note: * Modes 6 and 7 are not available on the ROMless version. 5.10.4 MOS Input Pull-Up Function
Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4, 5, and 6 when 8-bit bus mode is selected, or in mode 7, and can be specified as on or off on an individual bit basis. When a PEDDR bit is cleared to 0 in mode 4, 5, or 6 when 8-bit bus mode is selected, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode. The prior state is retained in software standby mode. Table 5.18 summarizes the MOS input pull-up states.
154
Table 5.18 MOS Input Pull-Up States (Port E)
Modes 7 4 to 6 8-bit bus 16-bit bus OFF OFF Reset OFF Hardware Standby Mode OFF Software Standby Mode ON/OFF In Other Operations ON/OFF
Legend OFF: MOS input pull-up is always off. ON/OFF: On when PEDDR = 0 and PEPCR = 1; otherwise off.
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5.11
5.11.1
Port F
Overview
Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQ, BACK, BREQO, CS4, and CS5), the system clock (o) output pin and interrupt input pins (IRQ0 to IRQ3). The interrupt input pins (IRQ0 to IRQ3) are Schmitt-triggered inputs. Figure 5.23 shows the port F pin configuration.
Port F pins PF7/o PF6/AS PF5/RD Port F PF4/HWR PF3/LWR/IRQ3 Pin functions in modes 4 to 6* PF7 (input)/o(output) PF6 (I/O)/AS (output) RD (output) HWR (output) PF3 (I/O)/LWR (output)/IRQ3 (input)
PF2/WAIT / IRQ2/ BREQO PF2 (I/O)/WAIT (input)/IRQ2 (input)/BREQO (output) PF1/BACK/IRQ1/ CS5 PF0/BREQ/IRQ0/ CS4 PF1 (I/O)/BACK (output)/IRQ1 (input)/CS5 (output) PF0 (I/O)/BREQ (input)/IRQ0 (input)/CS4 (output) Pin functions in mode 7* PF7 (input)/o (output) PF6 (I/O) PF5 (I/O) PF4 (I/O) PF3 (I/O)/IRQ3 (input) PF2 (I/O)/IRQ2 (input) PF1 (I/O)/IRQ1 (input) PF0 (I/O)/IRQ0 (input)
Note: * Modes 6 and 7 are not available on the ROMless version.
Figure 5.23 Port F Pin Functions
156
5.11.2
Register Configuration
Table 5.19 shows the port F register configuration. Table 5.19 Port F Registers
Name Port F data direction register Port F data register Port F register Bus control register L System control register Port function control register 1 Port function control register 2 Abbreviation PFDDR PFDR PORTF BCRL SYSCR PFCR1 PFCR2 R/W W R/W R R/W R/W R/W R/W Initial Value H'80/H'00* 2 H'00 Undefined H'3C H'01 H'0F H'30 Address* 1 H'FEBE H'FF6E H'FF5E H'FED5 H'FF39 H'FF45 H'FFAC
Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode.
Port F Data Direction Register (PFDDR)
Bit : 7 6 5 4 3 2 1 0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 4 to 6* Initial value : R/W Mode 7* Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W : 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6*, and to H'00 in mode 7*. It retains its prior state after in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become highimpedance when a transition is made to software standby mode. Note: * Modes 6 and 7 are not available on the ROMless version.
157
Port F Data Register (PFDR)
Bit : 7 PF7DR Initial value : R/W : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state after in software standby mode. Port F Register (PORTF)
Bit : 7 PF7 Initial value : R/W : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R 3 PF3 --* R 2 PF2 --* R 1 PF1 --* R 0 PF0 --* R
Note: * Determined by state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states, and cannot be modified. Writing of output data for the port F pins (PF7 to PF0) must always be performed on PFDR. If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and PFDR are initialized. PORTF retains its prior state after in software standby mode. Port Function Control Register 1 (PFCR1)
Bit : 7 CSS17 Initial value : R/W : 0 R/W 6 5 4 3 A23E 1 R/W 2 A22E 1 R/W 1 A21E 1 R/W 0 A20E 1 R/W
CSS36 PF1CS5S PF0CS4S 0 R/W 0 R/W 0 R/W
PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to H'0F by a reset, and in hardware standby mode. Bit 7--CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin. For details see section 5.12 port G.
158
Bit 6--CS36 Select (CSS36): Selects whether CS3 or CS6 is output from the PG1 pin. For details, see section 5.12 port G. Bit 5--Port F1 Chip Select 5 Select (PF1CS5S): Selects enabling or disabling of CS5 output. This bit is valid in modes 4 to 6.
Bit 5 PF1CS5S 0 1 Description PF1 is the PF1/BACK/IRQ1 pin (Initial value)
PF1 is the PF1/BACK/IRQ1/CS5 pin. CS5 output is enabled when BRLE = 0, CS25E = 1, and PF1DDR = 1
Bit 4--Port F0 Chip Select 4 Select (PF0CS4S): Selects enabling or disabling of CS4 output. This bit is valid in modes 4 to 6.
Bit 4 PF0CS4S 0 1 Description PF0 is the PF0/BREQ/IRQ0 pin (Initial value)
PF0 is the PF0/BREQ/IRQ0/CS4 pin. CS4 output is enabled when BRLE = 0, CS25E = 1, and PF0DDR = 1
Bit 3--Address 23 Enable (A23E): Enables or disables address output 23 (A23). For details, see section 5.2 port 1. Bit 2--Address 22 Enable (A22E): Enables or disables address output 22 (A22). For details, see section 5.2 port 1. Bit 1--Address 21 Enable (A21E): Enables or disables address output 21 (A21). For details, see section 5.2 port 1. Bit 0--Address 20 Enable (A20E): Enables or disables address output 20 (A20). For details, see section 5.2 port 1. Port Function Control Register 2 (PFCR2)
Bit : 7 -- Initial value : R/W : 0 R/W 6
--
5 CS167E 1 R/W
4 CS25E 1 R/W
3 ASOD 0 R/W
2 -- 0 R
1 -- 0 R
0 -- 0 R
0 R/W
PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to H'30 by a reset, and in hardware standby mode.
159
Bits 7 and 6--Reserved. Bit 5--CS167 Enable (CS167E): Enables or disables CS1, CS6, and CS7 output. For details, see section 5.12 port G. Bit 4--CS25 Enable (CS25E): Enables or disables CS2, CS3, CS4, and CS5 output. Change the CS25E setting only when the DDR bits are cleared to 0. This bit is valid in modes 4 to 6.
Bit 4 CS25E 0 1 Description CS2, CS3, CS4, and CS5 output disabled (can be used as I/O ports) CS2, CS3, CS4, and CS5 output enabled (Initial value)
Bit 3--AS Output Disable (ASOD): Enables or disables AS output. This bit is valid in modes 4 to 6.
Bit 3 ASOD 0 1 Description PF6 is used as AS output pin (Initial value)
PF6 is designated as I/O port, and does not function as AS output pin
Bits 2 to 0--Reserved. System Control Register (SYSCR)
Bit : 7 -- Initial value : R/W : 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 LWROD 0 R/W 1 -- 0 R/W 0 RAME 1 R/W
Bit 2--LWR Output Disable (LWROD): Enables or disables LWR output. This bit is valid in modes 4 to 6.
Bit 2 LWROD 0 1 Description PF3 is designated as LWR output pin (Initial value)
PF3 is designated as I/O port, and does not function as LWR output pin
160
Bus Control Register L (BCRL)
Bit : 7 BRLE Initial value : R/W : 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 -- 1 R/W 3 -- 1 R/W 2 -- 1 R/W 1 -- 0 R/W 0 WAITE 0 R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, selection of the area partition unit, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a reset, and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7 BRLE 0 1 Description External bus release disabled. BREQ, BACK, and BREQO pins can be used as I/O ports (Initial value) External bus release enabled
Bit 6--BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus-released state, or when an internal bus master performs an external space access.
Bit 6 BREQOE 0 1 Description BREQO output disabled. BREQO pin can be used as I/O port BREQO output enabled (Initial value)
Bit 0--WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin.
Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port Wait input by WAIT pin enabled (Initial value)
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5.11.3
Pin Functions
Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQ, BACK, BREQO, CS4, and CS5) the system clock (o) output pin and interrupt input pins (IRQ0 to IRQ3). The pin functions differ between modes 4, 5, and 6*1, and mode 7*1. Port F pin functions are shown in table 5.20. Table 5.20 Port F Pin Functions
Pin PF7/o Selection Method and Pin Functions The pin function is switched as shown below according to bit PF7DDR. PF7DDR Pin function 0 PF7 input pin 1 o output pin
PF6/AS
The pin function is switched as shown below according to the operating mode, and bit PF6DDR, and bit ASOD in PFCR2. Operating Mode ASOD PF6DDR Pin function 0 -- AS output pin 0 PF6 input pin Modes 1 4, 5, 6* 1 1 0
1 Mode 7*
-- 1 PF6 output pin
PF6 output PF6 input pin pin
PF5/RD
The pin function is switched as shown below according to the operating mode and bit PF5DDR. Operating Mode PF5DDR Pin function Modes 1 4, 5, 6* -- RD output pin 0 PF5 input pin Mode 7*
1
1 PF5 output pin
PF4/HWR
The pin function is switched as shown below according to the operating mode and bit PF4DDR. Operating Mode PF4DDR Pin function Modes 1 4, 5, 6* -- HWR output pin 0 PF4 input pin Mode 7*
1
1 PF4 output pin
162
Pin PF3/LWR/IRQ3
Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, and bit PF3DDR, and bit LWROD in SYSCR. Operating Mode LWROD PF3DDR Pin function 0 -- LWR output pin Modes 4, 5, 6 * 1 1* 3 0 PF3 input pin 1 PF3 output pin 0 Mode 7* 1 -- 1 PF3 output pin
PF3 input pin IRQ3 interrupt input pin* 2
PF2/WAIT/IRQ2/ BREQO
The pin function is switched as shown below according to the operating mode, and WAITE bit, BREQOE bit in BCRL and PF2DDR bit. Operating Mode BREQOE WAITE PF2DDR Pin function 0 PF2 input pin 0 1 0 PF2 WAIT output input pin pin Modes 4, 5, 6 * 1 0 1 1
Setting prohibited
Mode 7* 1 1 0 --
output pin
-- 1 --
prohibited
-- 0 PF2 input pin 1 PF2 output pin
BREQO Setting
IRQ2 interrupt input pin* 2
163
Pin PF1/BACK/IRQ1/ CS5
Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode, and the BRLE bit in BCRL, PF1CS5S bit in PFCR1, and CS25E bit in PFCR2 and PF1DDR bit. Operating Mode BRLE PF1DDR CS25E PF1CS5S Pin function 0 -- -- PF1 input pin 0 -- 0 PF1 output pin Modes 4, 5, 6 * 1 0 1 1 1 CS5 output pin 1 -- -- -- 0 -- -- PF1 input pin Mode 7* 1 -- 1 -- -- PF1 output pin
BACK output pin IRQ1 interrupt input pin* 2
PF0/BREQ/IRQ0/ The pin function is switched as shown below according to the operating mode, CS4 and the BRLE bit in BCRL and PF0CS4S bit in PFCR1 and CS25E bit in PFCR2 and PF0DDR bit. Operating Mode BRLE PF0DDR CS25E PF0CS4S Pin function 0 -- -- PF0 input pin 0 -- 0 PF0 output pin Modes 4, 5, 6 * 1 0 1 1 1 CS4 output pin 1 -- -- -- 0 -- -- PF0 input pin Mode 7* 1 -- 1 -- -- PF0 output pin
BREQ output pin IRQ0 interrupt input pin* 2
Notes: 1. Modes 6 and 7 are not available on the ROMless version. 2. When this pin is used as an external interrupt input, the pin function should be set as a port (PFn) input pin. 3. Valid only in 8-bit-bus mode.
164
5.12
5.12.1
Port G
Overview
Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3, CS6, CS7). The A/D converter input pin (ADTRG), and interrupt input pins (IRQ6, IRQ7). The interrupt input pins (IRQ6, IRQ7) are Schmitt-triggered inputs. Figure 5.24 shows the port G pin configuration.
Port G pins
PG4/CS0 PG3/CS1/ CS7 Port G PG2/CS2 PG1/CS3/IRQ7/ CS6 PG0/ADTRG/IRQ6
Pin functions in modes 4 to 6*
Pin functions in mode 7*
PG4 (I/O)/ CS0 (output) PG3 (I/O)/ CS1 (output)/ CS7 (output) PG2 (I/O)/ CS2 (output) PG1 (I/O)/ CS3 (output)/ IRQ7 (input)/ CS6 (output) PG0 (I/O)/ ADTRG (input)/ IRQ6 (input)
PG4 (I/O) PG3 (I/O) PG2 (I/O) PG1 (I/O)/ IRQ7 (input) PG0 (I/O)/ ADTRG (input)/ IRQ6 (input)
Note: * Modes 6 and 7 are not available on the ROMless version.
Figure 5.24 Port G Pin Functions
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5.12.2
Register Configuration
Table 5.21 shows the port G register configuration. Table 5.21 Port G Registers
Name Port G data direction register Port G data register Port G register Port function control register 1 Port function control register 2 Abbreviation PGDDR PGDR PORTG PFCR1 PFCR2 R/W W R/W R R/W R/W Initial Value* 1 H'10/H'00* 3 H'00 Undefined H'0F H'30 Address* 2 H'FEBF H'FF6F H'FF5F H'FF45 H'FFAC
Notes: 1. Value of bits 4 to 0. 2. Lower 16 bits of the address. 3. Initial value depends on the mode.
Port G Data Direction Register (PGDDR)
Bit : 7 -- Modes 4 and 5 Initial value : Undefined Undefined Undefined R/W : -- -- -- Modes 6 and 7* Initial value : Undefined Undefined Undefined R/W : -- -- -- 0 W 0 W 0 W 0 W 0 W 1 W 0 W 0 W 0 W 0 W 6 -- 5 -- 4 3 2 1 0
PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an undefined value will be read. The PGDDR is initialized by a reset and in hardware standby mode, to H'10 (bits 4 to 0) in modes 4 and 5, and to H'00 (bits 4 to 0) in modes 6 and 7*. It retains its prior state after in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. Note: * Modes 6 and 7 are not available on the ROMless version.
166
Port G Data Register (PGDR)
Bit : 7 -- 6 -- 5 -- 4 PG4DR 0 R/W 3 PG3DR 0 R/W 2 PG2DR 0 R/W 1 PG1DR 0 R/W 0 PG0DR 0 R/W
Initial value : Undefined Undefined Undefined R/W : -- -- --
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to PG0). Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. PGDR is initialized to H'00 (bits 4 to 0) by a reset, and in hardware standby mode. It retains its prior state after in software standby mode. Port G Register (PORTG)
Bit : 7 -- 6 -- 5 -- 4 PG4 --* R 3 PG3 --* R 2 PG2 --* R 1 PG1 --* R 0 PG0 --* R
Initial value : Undefined Undefined Undefined R/W : -- -- -- Note: * Determined by state of pins PG4 to PG0.
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port G pins (PG4 to PG0) must always be performed on PGDR. Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G read is performed while PGDDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORTG contents are determined by the pin states, as PGDDR and PGDR are initialized. PORTG retains its prior state after in software standby mode.
167
Port Function Control Register 1 (PFCR1)
Bit : 7 CSS17 Initial value : R/W : 0 R/W 6 5 4 3 A23E 1 R/W 2 A22E 1 R/W 1 A21E 1 R/W 0 A20E 1 R/W
CSS36 PF1CS5S PF0CS4S 0 R/W 0 R/W 0 R/W
PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to H'0F by a reset, and in hardware standby mode. Bit 7--CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin. Change the CSS17 bit setting only when the corresponding DDR bit is 0. This bit is valid in modes 4 to 6.
Bit 7 CSS17 0 1 Description PG3 is the PG3/CS1 pin. CS1 output is enabled when CS167E = 1 and PG3DDR = 1 (Initial value) PG3 is the PG3/CS7 pin. CS7 output is enabled when CS167E = 1 and PG3DDR = 1
Bit 6--CS36 Select (CSS36): Selects whether CS3 or CS6 is output from the PG1 pin. Change the CSS36 bit setting only when the corresponding DDR bit is 0. This bit is valid in modes 4 to 6.
Bit 6 CSS36 0 1 Description PG1 is the PG1/IRQ7/CS3 pin. CS3 output is enabled when CS25E = 1 and PG1DDR = 1 (Initial value) PG1 is the PG1/ IRQ7/CS6 pin. CS6 output is enabled when CS167E = 1 and PG1DDR = 1
Bit 5--Port F1 Chip Select 5 Select (PF1CS5S): Enables or disables CS5 output. For details, see section 5.11, Port F. Bit 4--Port F0 Chip Select 4 Select (PF0CS4S): Enables or disables CS4 output. For details, see section 5.11, Port F. Bit 3--Address 23 Enable (A23E): Enables or disables address output 23 (A23). For details, see section 5.2, Port 1. Bit 2--Address 22 Enable (A22E): Enables or disables address output 22 (A22). For details, see section 5.2,, Port 1.
168
Bit 1--Address 21 Enable (A21E): Enables or disables address output 21 (A21). For details, see section 5.2, Port 1. Bit 0--Address 20 Enable (A20E): Enables or disables address output 20 (A20). For details, see section 5.2, Port 1. Port Function Control Register 2 (PFCR2)
Bit : 7 -- Initial value : R/W : 0 R/W 6
--
5 CS167E 1 R/W
4 CS25E 1 R/W
3 ASOD 0 R/W
2 -- 0 R
1 -- 0 R
0 -- 0 R
0 R/W
PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to H'30 by a reset, and in hardware standby mode. This bit is valid in modes 4 to 6. Bits 7 and 6--Reserved. Bit 5--CS167 Enable (CS167E): Enables or disables CS1, CS6, and CS7 output. Change the CS167E setting only when the DDR bits are cleared to 0.
Bit 5 CS167E 0 1 Description CS1, CS6, and CS7 output disabled (can be used as I/O ports) CS1, CS6, and CS7 output enabled (Initial value)
Bit 4--CS25 Enable (CS25E): Enables or disables CS2, CS3, CS4, and CS5 output. Change the CS25E setting only when the DDR bits are cleared to 0. This bit is valid in modes 4 to 6.
Bit 4 CS25E 0 1 Description CS2, CS3, CS4, and CS5 output disabled (can be used as I/O ports) CS2, CS3, CS4, and CS5 output enabled (Initial value)
Bit 3--AS Output Disable (ASOD): Enables or disables AS output. This bit is valid in modes 4 to 6. For details, see section 5.11, Port F. Bits 2 to 0--Reserved.
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5.12.3
Pin Functions
Port G pins also function as bus control signal output pins (CS0 to CS3, CS6, CS7) the A/D converter input pin (ADTRG), and interrupt input pins (IRQ6, IRQ7). The pin functions are different in mode 7*, and modes 4 to 6*. Port G pin functions are shown in table 5.22. Table 5.22 Port G Pin Functions
Pin PG4/CS0 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode and bit PG4DDR. Operating Mode PG4DDR Pin function Modes 4, 5, 6 * 1 0 1 0 Mode 7* 1 1
PG4 input pin CS0 output pin PG4 input pin PG4 output pin
PG3/CS1/CS7
The pin function is switched as shown below according to the operating mode and CSS17 bit in PFCR1, CS167E bit in PFCR2, and bit PG3DDR. Operating Mode PG3DDR CS167E CSS17 Pin function 0 -- -- PG3 input pin 0 -- PG3 output pin 0 CS1 output pin Modes 4, 5, 6 * 1 1 1 1 CS7 output pin Mode 7* 1 0 -- -- PG3 input pin 1 -- -- PG3 output pin
PG2/CS2
The pin function is switched as shown below according to the operating mode and CS25E bit in PFCR2, and bit PG2DDR. Operating Mode PG2DDR CS25E Pin function 0 -- 0 Modes 4, 5, 6 * 1 1 1 0 -- Mode 7* 1 1 --
PG2 input PG2 output CS2 output PG2 input PG2 output pin pin pin pin pin
170
Pin PG1/CS3/CS6/ IRQ7
Selection Method and Pin Functions The pin function is switched as shown below according to the combination of operating mode and CSS36 bit in PFCR1, CS167E bit in PFCR2, CS25E bit and bit PG1DDR. Operating Mode PG1DDR CS167E CS25E CSS36 Pin function 0 -- -- --
PG1 input pin
Modes 4, 5, 6 * 1 1 0 0 --
PG1 pin
Mode 7* 1 0 1 -- 1 1 0
CS3 pin
2
1 -- -- --
PG1 output pin
1 0
CS3 pin
0 1 0
-- 1
CS6 pin
--
PG1 input pin
PG1 output pin
CS6 pin
output output
output output output
IRQ7 interrupt input pin*
PG0/ADTRG/IRQ6 The pin function is switched as shown below according to the combination of bits TRGS1 and TRGS0 (trigger select 1 and 0) in the A/D control register (ADCR). PG0DDR Pin function 0 PG0 input ADTRG input pin*
3
1 PG0 output
IRQ6 interrupt input pin* 2 Notes: 1. Modes 6 and 7 are not available on the ROMless version. 2. When this pin is used as an external interrupt input, it should not be used as an input/output pin with other functions. 3. ADTRG input when TRGS1 = TRGS0 = 1.
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5.13
5.13.1
Pin States
Port States in Each Mode
Table 5.23 I/O Port States in Each Processing State
Port Name Pin Name MCU Operating Mode Hardware Standby Software Mode Standby Mode T kept Bus-Released State kept Program Execution State Sleep Mode I/O port
Reset T
P17/TIOCB2/ 4 to 7 TCLKD P16/TIOCA2 P15/TIOCB1/ TCLKC P14/TIOCA1 P13/TIOGD0/ 4 to 6 TCLKB/A23 P12/TIOCC0/T CLKA/A22 P11/TIOCB0/ A21 P10/TIOCA0/ A20
T
T
[AnE = 0] kept [AnE * DDR = 1] kept [AnE * DDR * OPE = 1] T [AnE * DDR * OPE = 1] kept
[AnE = 0] kept [AnE * DDR = 1] kept [AnE * DDR = 1] T
[AnE = 0] I/O port [AnE * DDR = 1] I/O port [AnE * DDR = 1] Address output
7 Port 2 Port 3 P47/DA1 4 to 7 4 to 7 4 to 7
T T T T
T T T T
kept kept kept [DAOE1 = 1] kept [DAOE1 = 0] T
kept kept kept kept
I/O port I/O port I/O port I/O port
P46/DA0
4 to 7
T
T
[DAOE0 = 1] kept [DAOE0 = 0] T
kept
I/O port
P45 to P40
4 to 7
T
T
T
T
Input port
172
MCU Port Name Operating Pin Name Mode PA3/A19 PA2/A18 PA1/A17 PA0/A16 6 4, 5
Reset L
Hardware Standby Mode T
Software Standby Mode [OPE = 0] T [OPE = 1] kept
Bus-Released State T
Program Execution State Sleep Mode Address output
T
T
[DDR * OPE = 0] T [DDR * OPE = 1] kept
T
[DDR = 0] Input port [DDR = 1] Address output
7 Port B 4, 5
T L
T T
kept [OPE = 0] T [OPE = 1] kept
kept T
I/O port Address output
6
T
T
[DDR * OPE = 0] T [DDR * OPE = 1] kept
T
[DDR = 0] Input port [DDR = 1] Address output
7 Port C 4, 5
T L
T T
kept [OPE = 0] T [OPE = 1] kept
kept T
I/O port Address output
6
T
T
[DDR * OPE = 0] T [DDR * OPE = 1] kept
T
[DDR = 0] Input port [DDR = 1] Address output
7 Port D 4 to 6 7 Port E 4 to 8-bit 6 bus
T T T T
T T T T T T
kept T kept kept T kept
kept T kept kept T kept
I/O port Data bus I/O port I/O port Data bus I/O port
16-bit T bus 7 T
173
MCU Port Name Operating Pin Name Mode PF7 /o 4 to 6
Reset
Hardware Standby Software Mode Standby Mode [DDR = 0] Input port [DDR = 1] H
Bus-Released State [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output [ASOD = 1] kept [ASOD = 0] T
Program Execution State Sleep Mode [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output [ASOD = 1] I/O port [ASOD = 0] AS
Clock T output
7
T
T
[DDR = 0] Input port [DDR = 1] H
PF6/AS
4 to 6
H
T
[ASOD = 1] kept [ASOD * OPE = 1] T [ASOD * OPE = 1] H
7 PF5/RD PF4/HWR 4 to 6
T H
T T
kept [OPE = 0] T [OPE = 1] H
kept T
I/O port RD, HWR
7 PF3/LWR/ IRQ3 4 to 6
T H
T T
kept [LWROD = 1] kept
kept [LWROD = 1] kept
I/O port [LWROD = 1] I/O port [LWROD = 0] LWR
[LWROD * OPE = 1] [LWROD = 0] T T [LWROD * OPE = 1] H 7 PF2/WAIT / 4 to 6 IRQ2/ BREQO T T T T kept kept
I/O port
[BREQOE + WAITE [BREQOE + WAITE [BREQOE + WAITE = 0] = 0] = 0] kept kept I/O port [BREQOE = 1] kept [BREQOE = 0] And [WAITE * DDR = 1] T [BREQOE = 1] BREQO [BREQOE = 0] And [WAITE * DDR = 1] T kept [BREQOE = 1] BREQO [BREQOE = 0] And [WAITE * DDR = 1] WAIT I/O port
7
T
T
kept
174
MCU Port Name Operating Pin Name Mode PF1/BACK / 4 to 6 IRQ1/CS5
Reset T
Hardware Standby Mode T
Software Standby Mode [BRLE + CS25E * PF1CS5S = 0] kept [BRLE * DDR * CS25E * PF1CS5S =1] And [OPE = 0] T [BRLE * DDR * CS25E * PF1CS5S = 1] And [OPE = 1] H [BRLE = 1] BACK
Bus-Released State L
Program Execution State Sleep Mode [BRLE + CS25E * PF1CS5S = 0] I/O port [BRLE * DDR * CS25E * PF1CS5S =1] CS5 [BRLE = 1] BACK
7 PF0/BREQ/ 4 to 6 IRQ0/CS4
T T
T T
kept [BRLE + CS25E * PF0CS4S = 0] kept [BRLE * DDR * CS25E * PF0CS4S = 1] And [OPE = 0] T [BRLE * DDR * CS25E * PF0CS4S = 1] And [OPE = 1] H [BRLE = 1] T
kept T
I/O port [BRLE + CS25E * PF0CS4S = 0] I/O port [BRLE * DDR * CS25E * PF0CS4S = 1] CS4 [BRLE = 1] BREQ
7
T
T
kept
kept
I/O port
175
MCU Port Name Operating Pin Name Mode PG4/CS0 4, 5 6 7 PG3/CS1/ CS7 4 to 6
Reset H T T T
Hardware Standby Mode T
Software Standby Mode [DDR * OPE = 0] T [DDR * OPE = 1] H
Bus-Released State T
Program Execution State Sleep Mode [DDR = 0] Input port [DDR = 1] CS0
T T
kept [CS167E = 0] kept
kept [CS167E = 0] kept
I/O port [CS167E = 0] I/O port [CS167E * DDR = 1] Input port [CS167E * CSS17 * DDR = 1] CS1 [CS167E * CSS17 * DDR = 1] CS7
[CS167E * DDR = 1] [CS167E = 1] T T [CS167E * DDR * OPE = 1] T [CS167E * DDR * OPE = 1] H 7 PG2/CS2 4 to 6 T T T T kept [CS25E = 0] kept [CS25E * DDR = 1] T [CS25E * DDR * OPE = 1] T [CS25E * DDR * OPE = 1] H 7 T T kept kept kept [CS25E = 0] kept [CS25E = 1] T
I/O port [CS25E = 0] I/O port [CS25E * DDR = 1] Input port [CS25E * DDR = 1] CS2
I/O port
176
Port Name Pin Name PG1/CS3/ CS6/IRQ7
MCU Operating Mode Reset 4 to 6 T
Hardware Standby Mode T
Software Standby Mode [CSS36 * CS25E + CSS36 * CS167E = 0] kept [CSS36 * CS25E * DDR = 1] T [CSS36 * CS167E * DDR = 1] T [CSS36 * CS25E * DDR * OPE = 1] T [CSS36 * CS167E * DDR * OPE = 1] T [CSS36 * CS25E * DDR * OPE = 1] H [CSS36 * CS167E * DDR * OPE = 1] H
Bus-Released State [CSS36 * CS25E + CSS36 * CS167E = 0] kept [CSS36 * CS25E + CSS36 * CS167E = 1] T
Program Execution State Sleep Mode [CSS36 * CS25E + CSS36 * CS167E = 0] I/O port [CSS36 * CS25E * DDR = 1] Input port [CSS36 * CS167E * DDR = 1] Input port [CSS36 * CS25E * DDR = 1] CS3 [CSS36 * CS167E * DDR = 1] CS6
7 PG0/ADTRG/ 4 to 7 IRQ6
T T
T T
kept kept
kept kept
I/O port I/O port
Legend H: L: T: kept: DDR: OPE: WAITE: BRLE: BREQOE: AnE: ASOD: CS167E: CS25E: CSS36: CSS17: PF1CS5S: PF0CS4S: LWROD: DAOEn:
High level Low level High impedance Input port becomes high-impedance, output port retains state Data direction register Output port enable Wait input enable Bus release enable BREQO pin enable Address n enable (n = 23 to 20) AS output disable CS167 enable CS25 enable CS36 select CS17 select Port F1 chip select 5 select Port F0 chip select 4 select LWR output disable D/A output enable n (n = 0, 1) 177
5.14
5.14.1
I/O Port Block Diagrams
Port 1
Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 Modes 4 to 6 Bus controller AmE bit TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1
P1n
RPOR1
Internal address bus
Input capture input
WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 AmE: Address m enable n = 0 or 1 m = 20 or 21
Figure 5.25 (a) Port 1 Block Diagram (Pins P10 and P11)
178
Internal data bus
Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 Modes 4 to 6 Bus controller AmE bit TPU module Output compare output/ PWM output enable Output compare output/ PWM output
P1n
RDR1
RPOR1
Internal address bus
Input capture input External clock input
WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1: Read port 1 AmE: Address m enable n = 2 or 3 m = 22 or 23
Figure 5.25 (b) Port 1 Block Diagram (Pins P12 and P13)
Internal data bus
179
Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1
P1n
RDR1
RPOR1
Internal data bus TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input
WDDR1: WDR1: RDR1: RPOR1: n = 4 or 6
Write to P1DDR Write to P1DR Read P1DR Read port 1
Figure 5.25 (c) Port 1 Block Diagram (Pins P14 and P16)
180
Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1
P1n
RDR1
RPOR1
Internal data bus TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input External clock input
WDDR1: WDR1: RDR1: RPOR1: n = 5 or 7
Write to P1DDR Write to P1DR Read P1DR Read port 1
Figure 5.25 (d) Port 1 Block Diagram (Pins P15 and P17)
181
5.14.2
Port 2
Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2
P2n
RDR2
RPOR2
Internal data bus TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input
WDDR2: WDR2: RDR2: RPOR2: n = 0 to 7
Write to P2DDR Write to P2DR Read P2DR Read port 2
Figure 5.26 Port 2 Block Diagram (Pins P2n)
182
5.14.3
Port 3
Reset Internal data bus SCI module Serial transmit enable Serial transmit data RDR3 R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3
P3n
RPOR3
WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: n = 0 or 1
Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR
Notes: 1. Output enable signal 2. Open drain control signal
Figure 5.27 (a) Port 3 Block Diagram (Pins P30 and P31)
183
Reset R Q D P3nDDR C *1 WDDR3 Reset P3n R Q D P3nDR C *2 WDR3 Reset R Q D P3nODR C WODR3 RODR3
RDR3
RPOR3
Internal data bus SCI module Serial receive data enable Serial receive data
WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: n = 2 or 3
Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR
Notes: 1. Output enable signal 2. Open drain control signal
Figure 5.27 (b) Port 3 Block Diagram (Pins P32 and P33)
184
Reset R Q D P3nDDR C *1 WDDR3 Reset R Q D P3nDR C WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable
P3n
RPOR3
Internal data bus Serial clock input Interrupt controller IRQ interrupt input
WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: n = 4 or 5
Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR
Notes: 1. Output enable signal 2. Open drain control signal
Figure 5.27 (c) Port 3 Block Diagram (Pins P34 and P35)
185
5.14.4
Port 4
Internal data bus A/D converter module Analog input Internal data bus A/D converter module Analog input D/A converter module Output enable Analog output
RPOR4 P4n
RPOR4: Read port 4 n = 0 to 5
Figure 5.28 (a) Port 4 Block Diagram (Pins P40 to P45)
RPOR4 P4n
RPOR4: Read port 4 n = 6 or 7
Figure 5.28 (b) Port 4 Block Diagram (Pins P46 and P47)
186
5.14.5
Port A
Modes 6 and 7
Reset R Q D PAnPCR C WPCRA RPCRA
Internal data bus
Reset Modes 4 and 5 R Q D PAnDDR C WDDRA Reset R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA
*1
PAn
Mode 7 Modes 4 to 6
RDRA
RPORA WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: n = 0 to 3 Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR
Notes: 1. Output enable signal 2. Open drain control signal
Figure 5.29 Port A Block Diagram (Pins PA0, PA1, PA2, and PA3)
187
Internal address bus
5.14.6
Port B
Modes 6 and 7
Reset Internal address bus Internal data bus R Q D PBnPCR C WPCRB RPCRB
Reset Modes 4 and 5 R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB
PBn
Mode 7 Modes 4 to 6
RDRB
RPORB
WDDRB: WDRB: WPCRB: RDRB: RPORB: RPCRB: n = 0 to 7
Write to PBDDR Write to PBDR Write to PBPCR Read PBDR Read port B Read PBPCR
Figure 5.30 Port B Block Diagram (Pins PBn)
188
5.14.7
Port C
Modes 6 and 7
Reset R Q D PCnPCR C WPCRC RPCRC
Reset Modes 4 and 5 R Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC
PCn
Mode 7 Modes 4 to 6
RDRC
RPORC
WDDRC: WDRC: WPCRC: RDRC: RPORC: RPCRC: n = 0 to 7
Write to PCDDR Write to PCDR Write to PCPCR Read PCDR Read port C Read PCPCR
Figure 5.31 Port C Block Diagram (Pins PCn)
Internal address bus
Internal data bus
189
5.14.8
Port D
Reset R Q D PDnPCR C WPCRD RPCRD
Internal upper data bus
Mode 7 Reset R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD
External address write Modes 4 to 6
PDn
Mode 7 Modes 4 to 6
External address upper write External address lower write
RDRD
RPORD
WDDRD: WDRD: WPCRD: RDRD: RPORD: RPCRD: n = 0 to 7
Write to PDDDR Write to PDDR Write to PDPCR Read PDDR Read port D Read PDPCR
External address upper read
External address lower read
Figure 5.32 Port D Block Diagram (Pins PDn)
190
Internal lower data bus
5.14.9
Port E
Internal upper data bus
R Q D PEnPCR C WPCRE RPCRE Mode 7
Reset R Q D PEnDDR C WDDRE Modes 4 to 6 Reset R Q D PEnDR C WDRE
External address write
PEn
Modes 4 to 6
RDRE
RPORE
External address lower read WDDRE: WDRE: WPCRE: RDRE: RPORE: RPCRE: n = 0 to 7 Write to PEDDR Write to PEDR Write to PEPCR Read PEDR Read port E Read PEPCR
Figure 5.33 Port E Block Diagram (Pins PEn)
191
Internal lower data bus Bus controller 8-bit bus mode
Reset
5.14.10
Port F
Reset R Q D PF0DDR C WDDRF Modes 4 to 6 Reset PF0 R Q D PF0DR C WDRF
Internal data bus
Port CS25E bit PF0CS4S bit Bus controller BRLE bit
Chip select RDRF
RPORF
Bus request input WDDRF: WDRF: RDRF: RPORF: CS25E: PF0CS4S: BRLE: Write to PFDDR Write to PFDR Read PFDR Read port F CS25 enable Port F0 chip select 4 select Bus release enable Interrupt controller IRQ interrupt input
Figure 5.34 (a) Port F Block Diagram (Pin PF0)
192
Reset R Q D PF1DDR C WDDRF Reset R Q D PF1DR C WDRF Modes 4 to 6
PF1
RDRF
RPORF Port CS25E bit PF1CS5S bit Interrupt controller IRQ interrupt input
WDDRF: WDRF: RDRF: RPORF: CS25E: PF1CS5S: BRLE:
Write to PFDDR Write to PFDR Read PFDR Read port F CS25 enable Port F1 chip select 5 select Bus release enable
Figure 5.34 (b) Port F Block Diagram (Pin PF1)
Internal data bus Bus controller BRLE bit Bus request acknowledge output Chip select
193
Reset R Q D PF2DDR C WDDRF Reset R Q D PF2DR C WDRF
PF2
Modes 4 to 6
Internal data bus Bus controller Wait enable Bus request output enable Bus request output Wait input Interrupt controller IRQ Interupt input
Modes 4 to 6
RDRF
RPORF
WDDRF: WDRF: RDRF: RPORF:
Write to PFDDR Write to PFDR Read PFDR Read port F
Figure 5.34 (c) Port F Block Diagram (Pin PF2)
194
Reset R Q D PF3DDR C WDDRF Mode 7 PF3 Modes 4 to 6 Reset R Q D PF3DR C WDRF
LWROD bit
Modes 4 to 6
RDRF
RPORF
WDDRF: WDRF: RDRF: RPORF: LWROD:
Write to PFDDR Write to PFDR Read PFDR Read port F LWR output disable
Internal data bus Bus controller LWR output Interrupt controller IRQ interrupt input
Figure 5.34 (d) Port F Block Diagram (Pin PF3)
195
Reset R Q D PF4DDR C WDDRF Mode 7 PF4 Modes 4 to 6 Reset R Q D PF4DR C WDRF
Modes 4 to 6
RDRF
RPORF
WDDRF: WDRF: RDRF: RPORF:
Write to PFDDR Write to PFDR Read PFDR Read port F
Figure 5.34 (e) Port F Block Diagram (Pin PF4)
196
Internal data bus Bus controller HWR output
Reset R Q D PF5DDR C WDDRF Mode 7 PF5 Modes 4 to 6 Reset R Q D PF5DR C WDRF
Modes 4 to 6
RDRF
RPORF
WDDRF: WDRF: RDRF: RPORF:
Write to PFDDR Write to PFDR Read PFDR Read port F
Figure 5.34 (f) Port F Block Diagram (Pin PF5)
Internal data bus Bus controller RD output
197
Reset Internal data bus
ASOD bit
Modes 4 to 6
R Q D PF6DDR C WDDRF Reset R Q D PF6DR C WDRF
Mode 7
PF6 Modes 4 to 6
Bus controller AS output RDRF
RPORF
WDDRF: WDRF: RDRF: RPORF: ASOD:
Write to PFDDR Write to PFDR Read PFDR Read port F AS output disable
Figure 5.34 (g) Port F Block Diagram (Pin PF6)
198
Reset Modes 4 to 6 Mode 7
WDDRF Reset R Q D PF7DR C WDRF
PF7
Internal data bus
o
S R Q D D PF7DDR C
RDRF
RPORF
WDDRF: WDRF: RDRF: RPORF:
Write to PFDDR Write to PFDR Read PFDR Read port F
Figure 5.34 (h) Port F Block Diagram (Pin PF7)
199
5.14.11
Port G
Reset Internal data bus A/D convereter A/D converter external trigger input Interrput controller IRQ interrupt input R Q D PG0DDR C WDDRG Reset PG0 R Q D PG0DR C WDRG
RDRG
RPORG
WDDRG: WDRG: RDRG: RPORG:
Write to PGDDR Write to PGDR Read PGDR Read port G
Figure 5.35 (a) Port G Block Diagram (Pin PG0)
200
Reset R Q D PG1DDR C WDDRG Mode 7 PG1 Modes 4 to 6 Reset R Q D PG1DR C WDRG
Internal data bus Port CS167E bit CSS36 bit CS25E bit Bus controller Chip select 3 Chip select 6
RDRG
RPORG
WDDRG: WDRG: RDRG: RPORG: CS25E: CS167E: CSS36:
Write to PGDDR Write to PGDR Read PGDR Read port G CS25 enable CS167 enable CS36 select
Figure 5.35 (b) Port G Block Diagram (Pin PG1)
201
Reset R Q D PG2DDR C WDDRG Mode 7 PG2 Modes 4 to 6 Reset R Q D PG2DR C WDRG
Internal data bus Port CS25E bit Bus controller Chip select 2
RDRG
RPORG
WDDRG: WDRG: RDRG: RPORG: CS25E:
Write to PGDDR Write to PGDR Read PGDR Read port G CS25 enable
Figure 5.35 (c) Port G Block Diagram (Pin PG2)
202
Reset R Q D PG3DDR C WDDRG Mode 7 PG3 Modes 4 to 6 Reset R Q D PG3DR C WDRG Port CS167E bit CSS17 bit Bus controller Chip select 1 Chip select 7 RDRG
RPORG
WDDRG: WDRG: RDRG: RPORG: CS167E: CSS17:
Write to PGDDR Write to PGDR Read PGDR Read port G CS167 enable CS17 select
Figure 5.35 (d) Port G Block Diagram (Pin PG3)
Internal data bus
203
Modes 4 and 5 Reset
Modes 6 and 7
WDDRG Mode 7 PG4 Modes 4 to 6 Reset R Q D PG4DR C WDRG
Internal data bus Bus controller Chip select 0
SR D Q PG4DDR C
RDRG
RPORG
WDDRG: WDRG: RDRG: RPORG:
Write to PGDDR Write to PGDR Read PGDR Read port G
Figure 5.35 (e) Port G Block Diagram (Pin PG4)
204
Section 6 Supporting Module Block Diagrams
6.1
6.1.1 * * * * *
Interrupt Controller
Features
Selection of two interrupt control modes Eight priority levels can be set for each module with IPR Independent vector addresses (NMI, IRQ7 to IRQ0) Nine external interrupt pins DTC activation control Block Diagram
6.1.2
INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit Interrupt request IRQ input unit ISR ISCR IER Priority determination I I2 to I0 Vector number
CPU
Internal interrupt source SWDTEND to TEI
CCR EXR
IPR Interrupt controller
Legend ISCR: IER: ISR: IPR: SYSCR:
IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register
Figure 6.1 Block Diagram of Interrupt Controller
205
6.1.3 Table 6.1
Name
Pins Interrupt Controller Pins
Symbol NMI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected
Nonmaskable interrupt
External interrupt requests 7 to 0
IRQ7 to IRQ0
Input
6.2
6.2.1 * * * * * * * *
Data Transfer Controller
Features
Transfer possible over any number of channels Variety of transfer modes, including normal, repeat, and block transfer Direct specification of 16-Mbyte address space possible Byte or word can be selected as the transfer unit A CPU interrupt can be requested for an interrupt that activates the DTC Can be activated by software Module stop mode can be set DTC register information is located in on-chip RAM
206
6.2.2
Block Diagram
Internal address bus
Interrupt controller
DTC
On-chip RAM
DTCERA to DTCERE
DTVECR
Interrupt request
MRA MRB CRA CRB
DTC activation request
CPU interrupt request
Internal data bus
Legend MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERE: DTVECR:
DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC destination address register DTC enable registers A to E DTC vector register
Note: The RAME bit in SYSCR must be set to 1 when the DTC is used.
Figure 6.2 Block Diagram of DTC
DAR SAR
Control logic
Register information
207
6.3
6.3.1 * * * * * * * * * *
16-Bit Timer Pulse Unit
Features
Comprises six 16-bit timer channels Maximum 16 pulse inputs/outputs Selection of 8 counter input clocks for each channel Compare match, input capture, counter clear operation, synchronous operation, and PWM mode can be set for each channel Buffer operation can be set for channels 0 and 3 Phase counting mode can be set independently for each of channels 1, 2, 4, and 5 Cascaded operation possible by connecting two 16-bit counter channels to form a 32-bit counter Fast access via internal 16-bit bus A/D converter conversion start trigger can be generated Module stop mode can be set
208
6.3.2
Block Diagram
TCR TMDR TIORH TIORL TIER TSR
Channel 3
TCNT TGRA TGRB TGRC TGRD
Control logic for channels 3 to 5
[Input/output pins] TIOCA3 Channel 3: TIOCB3 TIOCC3 TIOCD3 TIOCA4 Channel 4: TIOCB4 Channel 5: TIOCA5 TIOCB5
TCR TMDR TIOR TIER TSR
Channel 5
TCR TMDR TIORH TIORL TIER TSR
Channel 0
[Clock input] Internal clock: o/1 o/4 o/16 o/64 o/256 o/1024 o/4096 External clock:TCLKA TCLKB TCLKC TCLKD
Module data bus
TSTR TSYR
Control logic
TCNT TGRA TGRB
[Interrupt request signals] Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U
TMDR
Channel 4
TSR
TCR TIOR TIER
TCNT TGRA TGRB
Common
Bus interface
Internal data bus A/D conversion start request signal
TCNT TGRA TGRB TGRC TGRD
Control logic for channels 0 to 2
TCR TMDR TIOR TIER TSR
[Input/output pins] TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 Channel 2: TIOCA2 TIOCB2
[Interrupt request signals] Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U
TCR TMDR TIOR TIER TSR
Channel 1
Channel 2
Figure 6.3 Block Diagram of TPU
TCNT TGRA TGRB
TCNT TGRA TGRB
209
6.3.3 Table 6.2
Channel All
Pins TPU Pins
Name Clock input A Symbol TCLKA I/O Input Function External clock A input pin (Channel 1 and 5 phase counting mode A-phase input) External clock B input pin (Channel 1 and 5 phase counting mode B-phase input) External clock C input pin (Channel 2 and 4 phase counting mode A-phase input) External clock D input pin (Channel 2 and 4 phase counting mode B-phase input) TGR0A input capture input/output compare output/PWM output pin TGR0B input capture input/output compare output/PWM output pin TGR0C input capture input/output compare output/PWM output pin TGR0D input capture input/output compare output/PWM output pin TGR1A input capture input/output compare output/PWM output pin TGR1B input capture input/output compare output/PWM output pin TGR2A input capture input/output compare output/PWM output pin TGR2B input capture input/output compare output/PWM output pin TGR3A input capture input/output compare output/PWM output pin TGR3B input capture input/output compare output/PWM output pin TGR3C input capture input/output compare output/PWM output pin TGR3D input capture input/output compare output/PWM output pin
Clock input B
TCLKB
Input
Clock input C
TCLKC
Input
Clock input D
TCLKD
Input
0
Input capture/out compare match A0 Input capture/out compare match B0 Input capture/out compare match C0 Input capture/out compare match D0
TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
1
Input capture/out compare match A1 Input capture/out compare match B1
2
Input capture/out compare match A2 Input capture/out compare match B2
3
Input capture/out compare match A3 Input capture/out compare match B3 Input capture/out compare match C3 Input capture/out compare match D3
210
Channel 4
Name Input capture/out compare match A4 Input capture/out compare match B4
Symbol TIOCA4 TIOCB4 TIOCA5 TIOCB5
I/O I/O I/O I/O I/O
Function TGR4A input capture input/output compare output/PWM output pin TGR4B input capture input/output compare output/PWM output pin TGR5A input capture input/output compare output/PWM output pin TGR5B input capture input/output compare output/PWM output pin
5
Input capture/out compare match A5 Input capture/out compare match B5
6.4
6.4.1 * * * * * * * *
8-Bit Timer
Features
Two-channel timer using 8-bit counters as base Selection of four counter input clocks Counter clearing can be specified Timer output by combination of two compare match signals Cascaded operation possible by connecting both counter channels to form a 16-bit counter Three interrupt sources for each channel A/D converter conversion start trigger can be generated Module stop mode can be set
211
6.4.2
Block Diagram
External clocks TMCI0 TMCI1
Internal clocks o/8 o/64 o/8192
Clock selection
Clock 1 Clock 0 TCORA0 Compare match A1 Compare match A0 Comparator A0 Overflow 1 Overflow 0 Clear 0 Clear 1 Compare match B1 Compare match B0 Comparator B0 TCORA1
Comparator A1
TMO0 TMRI0
TCNT0
TCNT1
Internal bus
TMO1 TMRI1
Control logic
Comparator B1
TCORB0
TCORB1
A/D conversion start request signal
TCSR0
TCSR1
TCR0 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals
TCR1
Figure 6.4 Block Diagram of 8-Bit Timer
212
6.4.3 Table 6.3
Channel 0
Pins 8-Bit Timer Pins
Name Timer output pin 0 Timer clock input pin 0 Timer reset input pin 0 Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 I/O Output Input Input Output Input Input Function Compare match output Counter external clock input Counter external reset input Compare match output Counter external clock input Counter external reset input
1
Timer output pin 1 Timer clock input pin 1 Timer reset input pin 1
213
6.5
6.5.1 * * * *
Watchdog Timer
Features
Switchable between watchdog timer mode and interval timer mode WDTOVF output in watchdog timer mode Interrupt generation when counter overflows in interval timer mode Selection of eight counter input clocks Block Diagram
6.5.2
Overflow WOVI (interrupt request signal) Interrupt control Clock Clock selection
WDTOVF*2 Internal reset signal*1
Reset control
o/2 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Internal clocks
RSTCSR
TCNT
TSCR
Module bus
Bus interface
WDT Legend TCSR: TCNT: RSTCSR:
Timer control/status register Timer counter Reset control/status register
Notes: 1. The internal reset signal can be generated by means of a register setting. 2. The WDTOVF pin function cannot be used in the F-ZTAT version.
Figure 6.5 Block Diagram of WDT
214
Internal bus
6.5.3 Table 6.4
Name
Pins WDT Pin
Symbol WDTOVF* I/O Output Function Outputs counter overflow signal in watchdog timer mode
Watchdog timer overflow
Note: * The WDTOVF pin function cannot be used in the F-ZTAT version.
6.6
6.6.1 * * * * * * * *
Serial Communication Interface
Features
Two on-chip channels in the H8S/2319 and H8S/2318 Series Selection of synchronous or asynchronous serial communication mode Full-duplex communication capability Selection of LSB-first or MSB-first transfer Built-in baud rate generator allows any bit rate to be selected Selection of transmit/receive clock source Four interrupts (ERI, RXI, TXI, and TEI), of which RXI and TXI can activate the DTC Module stop mode can be set
215
6.6.2
Block Diagram
Bus interface
Module data bus
Internal data bus
RDR
TDR
SCMR SSR SCR
BRR o Baud rate generator o/4 o/16 o/64
RxD
RSR
TSR
SMR Transmission/ reception control
TxD Parity generation Parity check SCK
Clock
External clock TEI TXI RXI ERI Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register
Legend SCMR: RSR: RDR: TSR: TDR: SMR: SCR: SSR: BRR:
Figure 6.6 Block Diagram of SCI
216
6.6.3 Table 6.5
Channel 0
Pins SCI Pins
Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 I/O I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output
1
Serial clock pin 1 Receive data pin 1 Transmit data pin 1
217
6.7
6.7.1 * * * *
Smart Card Interface
Features
IC card interface conforming to ISO/IEC7816-3 supported as SCI extension function Switching between normal SCI and smart card interface by means of register setting Built-in baud rate generator allows any bit rate to be selected Three interrupts (TXI, RXI, and ERI), of which RXI and TXI can activate the DTC Block Diagram
6.7.2
Bus interface
Module data bus
Internal data bus
RDR
TDR
RxD
RSR
TSR
TxD
SCMR SSR SCR SMR Transmission/ reception control
BRR o o/4 o/16 o/64
Baud rate generator
Parity generation Parity check
SCK
Clock
Legend SCMR: RSR: RDR: TSR: TDR: SMR: SCR: SSR: BRR:
TXI RXI ERI
Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register
Figure 6.7 Block Diagram of Smart Card Interface
218
6.7.3 Table 6.6
Channel 0
Pins Smart Card Interface Pins
Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 I/O I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output
1
Serial clock pin 1 Receive data pin 1 Transmit data pin 1
6.8
6.8.1 * * * * * * * * * *
A/D Converter (8 Analog Input Channel Version)
Features
10-bit resolution 8 input channels Settable analog conversion voltage range Conversion time: 6.7 s per channel (at 20 MHz operation) Selection of single mode or scan mode as operating mode Four data registers Sample-and-hold function Three kinds of conversion start (software, timer conversion start trigger, or ADTRG pin) A/D conversion end interrupt request generation Module stop mode can be set
219
6.8.2
Block Diagram
Module data bus
Bus interface ADDRC ADDRD ADDRA ADCSR ADDRB
Internal data bus
AVCC Vref AVSS 10-bit D/A
Successive-approximations register
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
+
Multiplexer
- Comparator Sample-and-hold circuit
ADI interrupt signal Conversion start trigger from 8-bit timer or TPU
Control circuit
ADTRG
Legend ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD:
A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D
Figure 6.8 Block Diagram of A/D Converter
220
ADCR
6.8.3 Table 6.7
Name
Pins A/D Converter Pins
Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input External trigger for starting A/D conversion Group 1 analog input Function Analog circuit power supply Analog circuit ground and reference voltage A/D conversion reference voltage Group 0 analog input
Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin
221
6.9
6.9.1 * * * * * *
D/A Converter
Features
8-bit resolution Two output channels Maximum conversion time of 10 s (with 20 pF capacitive load) Output voltage of 0 V to Vref D/A output hold function in software standby mode Module stop mode can be set Block Diagram
6.9.2
Module data bus Bus interface Vref DADR0 DADR1 AVCC DA1 DA0 AVSS 8-bit D/A Control circuit Legend DACR: DADR0, DADR1: D/A control register D/A data registers 0 and 1
Internal data bus
Figure 6.9 Block Diagram of D/A Converter
222
DACR
6.9.3 Table 6.8
Name
Pins D/A Converter Pins
Symbol AVCC AVSS DA0 DA1 Vref I/O Input Input Output Output Input Function Analog circuit power supply Analog circuit ground and reference voltage Channel 0 analog output Channel 1 analog output Analog circuit reference voltage
Analog power supply pin Analog ground pin Analog output pin 0 Analog output pin 1 Reference voltage pin
223
6.10
6.10.1
RAM
Features
* Eight kbytes of on-chip high-speed static RAM in the H8S/2319, H8S/2318, H8S/2317, H8S/2316, H8S/2315, and H8S/2312, and two kbytes in the H8S/2313, H8S/2311, and H8S/2310 * Connected to the CPU by a 16-bit data bus, enabling one-state access to both byte data and word data * Can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR) 6.10.2 Block Diagram
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFDC00 H'FFDC02 H'FFDC04
H'FFDC01 H'FFDC03 H'FFDC05
H'FFFBFE
H'FFFBFF
Figure 6.10 Block Diagram of RAM (8 kbytes)
224
6.11
6.11.1
ROM (H8S/2319)
Features
* Connected to the bus master by a 16-bit data bus, enabling one-state access to both byte data and word data * The flash memory version (H8S/2319 F-ZTAT) can be erased and programmed with a PROM programmer, as well as on-board 6.11.2 Block Diagrams
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000 H'000002
H'000001 H'000003
H'07FFFE
H'07FFFF
Figure 6.11 Block Diagram of Flash Memory (512 kbytes)
225
Internal address bus
Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER SYSCR2 Bus interface/controller Operating mode Mode pins
Flash memory (512 kbytes)
Legend FLMCR1: FLMCR2: EBR1: EBR2: RAMER: SYSCR2:
Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register System control register 2
Figure 6.12 Block Diagram of Flash Memory
226
6.12
6.12.1
ROM
Features
* Connected to the bus master by a 16-bit data bus, enabling one-state access to both byte data and word data * The flash memory version (256 kbytes in the H8S/2318 F-ZTAT and 384 kbytes in the H8S/2315 F-ZTAT) can be erased and programmed with a PROM programmer, as well as onboard * The H8S/2318 has 256 kbytes, the H8S/2317 128 kbytes, the H8S/2316 and H8S/2313 64 kbytes, and the H8S/2311 32 kbytes, of on-chip mask ROM 6.12.2 Block Diagrams
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000 H'000002
H'000001 H'000003
H'03FFFE
H'03FFFF
Figure 6.13 Block Diagram of Mask ROM (256 kbytes)
227
Internal address bus
Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER SYSCR2 Bus interface/controller Operating mode FWE pin Mode pins
Flash memory (256 kbytes/384 kbytes)
Legend FLMCR1: FLMCR2: EBR1: EBR2: RAMER: SYSCR2:
Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register System control register 2
Figure 6.14 Block Diagram of Flash Memory
228
6.13
6.13.1
Clock Pulse Generator
Features
* Comprises an oscillator, duty correction circuit, medium-speed clock divider, and bus master clock selection circuit * Generates system clock (o), bus master clock, and internal clock * Allows switching between medium-speed mode and variable clock division function 6.13.2 Block Diagram
SCKCR SCK2 to SCK0 DIV EXTAL Oscillator XTAL Duty correction circuit Mediumspeed clock divider Bus master clock selection circuit
o/2 to o/32
System clock To o pin
Internal clock To on-chip supporting modules
Bus master clock To CPU and DTC
Figure 6.15 Block Diagram of Clock Pulse Generator
229
230
Section 7 Electrical Characteristics
Note: Please contact a Hitachi sales agency for the electrical characteristics of the H8S/2319 F-ZTAT version.
7.1
Electrical Characteristics of Mask ROM Version (H8S/2318, H8S/2317, H8S/2316, H8S/2313, H8S/2311) and ROMless Version (H8S/2312, H8S/2310)
Absolute Maximum Ratings
7.1.1
Table 7.1 lists the absolute maximum ratings. Table 7.1
Item Power supply voltage Input voltage (except port 4) Input voltage (port 4) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature
Absolute Maximum Ratings
Symbol VCC Vin Vin Vr ef AVCC VAN Topr Value -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.3 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Unit V V V V V V C C C
Storage temperature
Tstg
-55 to +125
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
231
7.1.2 Table 7.2
DC Characteristics DC Characteristics
Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications)
Item Schmitt Ports 1, 2, trigger input IRQ0 to IRQ7 voltage Input high voltage Symbol VT - VT +
+ -
Min VCC x 0.2 -- VCC x 0.9 VCC x 0.7 2.2 2.2
Typ -- --
Max -- VCC x 0.7 -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.1 VCC x 0.2 -- -- 0.4 10.0 1.0 1.0 1.0
Unit V V V V V V
Test Conditions
VT - VT VCC x 0.07 -- -- -- -- -- -- -- -- -- -- -- -- -- --
RES, STBY, NMI, VIH MD2 to MD0 EXTAL Ports 3, A to G Port 4
AVCC + 0.3 V V V V V V A A A A Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V I OH = -200 A I OH = -1 mA I OL = 1.6 mA Vin = 0.5 to VCC - 0.5 V
Input low voltage
RES, STBY, MD2 to MD0 NMI, EXTAL, ports 3, 4, A to G
VIL
-0.3 -0.3
Output high All output pins voltage Output low voltage Input leakage current All output pins RES STBY, NMI, MD2 to MD0 Port 4 Three-state Ports 1, 2, 3, A to G leakage current (off state)
VOH
VCC - 0.5 VCC - 1.0
VOL | Iin |
-- -- -- --
| ITSI |
--
232
Item Input pull-up Ports A to E MOS current Input RES capacitance NMI All input pins except RES and NMI Current dissipation*
2
Symbol Min -I p Cin 10 -- -- --
Typ -- -- -- --
Max 300 30 30 15
Unit A pF pF pF
Test Conditions Vin = 0V Vin = 0 V f = 1 MHz Ta = 25C
Normal operation
I CC* 4
--
35 (3.0 V) 50 (3.3 V)
80 100 64 80 10 80 2.0 5.0 3.0 5.0 --
mA mA mA mA A
f = 20 MHz f = 25 MHz f = 20 MHz f = 25 MHz Ta 50C 50C < Ta
Sleep mode
--
25 (3.0 V) 35 (3.3 V)
Standby mode*
3
-- --
0.01 -- 0.2 (3.0 V) 0.01 1.4 (3.0 V) 0.01 --
Analog power supply voltage Reference power supply voltage
During A/D and D/A conversion Idle During A/D and D/A conversion Idle
AI CC
-- --
mA A mA A V
AI CC
-- --
RAM standby voltage
VRAM
2.0
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to V CC, and the AVSS pin to VSS . 2. Current dissipation values are for V IH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and all MOS input pull-ups in the off state. 3. The values are for VRAM V CC < 2.7 V, VIH min = VCC x 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 1.10 (mA/(MHz x V)) x V CC x f (normal operation) I CC max = 1.0 (mA) + 0.88 (mA/(MHz x V)) x V CC x f (sleep mode)
233
Table 7.3
Permissible Output Currents
Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins All output pins Total of all output pins Symbol I OL IOL -I OH -IOH Min -- -- -- -- Typ -- -- -- -- Max 2.0 80 2.0 40 Unit mA mA mA mA
Note: To protect chip reliability, do not exceed the output current values in table 7.3.
7.1.3
AC Characteristics
3V
RL Chip output pin C RH C = 50 pF: ports 1, A to F C = 30 pF: ports 2, 3, G RL = 2.4 k RH = 12 k Input/output timing measurement level: 1.5 V (VCC = 2.7 V to 3.6 V)
Figure 7.1 Output Load Circuit
234
(1) Clock Timing Table 7.4 Clock Timing
Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Clock cycle time Clock pulse high width Clock pulse low width Clock rise time Clock fall time Reset oscillation stabilization time (crystal) Software standby oscillation stabilization time (crystal) External clock output stabilization delay time Symbol t cyc t CH t CL t Cr t Cf t OSC1 t OSC2 t DEXT Min 50 20 20 -- -- 10 10 500 Max 500 -- -- 5 5 -- -- -- Condition B Min 40 15 15 -- -- 10 10 500 Max 500 -- -- 5 5 -- -- -- Unit ns ns ns ns ns ms ms s Figure 7.3 Figure 7.3 Test Conditions Figure 7.2
235
tcyc
tCH tCf
o
tCL
tCr
Figure 7.2 System Clock Timing
EXTAL tDEXT VCC tDEXT
STBY
NMI tOSC1 RES tOSC1
o
Figure 7.3 Oscillation Stabilization Timing
236
(2) Control Signal Timing Table 7.5 Control Signal Timing
Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (in recovery from software standby mode) IRQ setup time IRQ hold time IRQ pulse width (in recovery from software standby mode) Symbol t RESS t RESW t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW Min 200 20 150 10 200 150 10 200 Max -- -- -- -- -- -- -- -- Condition B Min 200 20 150 10 200 150 10 200 Max -- -- -- -- -- -- -- -- ns Unit ns t cyc ns Figure 7.5 Test Conditions Figure 7.4
237
o tRESS RES tRESW tRESS
Figure 7.4 Reset Input Timing
o tNMIS NMI tNMIW tNMIH
IRQ tIRQW tIRQS IRQ edge input tIRQS IRQ level input tIRQH
Figure 7.5 Interrupt Input Timing
238
(3) Bus Timing Table 7.6 Bus Timing
Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Address delay time Address setup time Address hold time CS delay time 1 AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Symbol tAD tAS tAH tCSD1 tASD tRSD1 tRSD2 tRDS tRDH Min -- 0.5 x tcyc - 15 0.5 x tcyc - 10 -- -- -- -- 15 0 -- -- -- -- -- Max 20 -- -- 20 20 20 20 -- -- 1.0 x tcyc - 25 1.5 x tcyc - 25 2.0 x tcyc - 25 2.5 x tcyc - 25 3.0 x tcyc - 25 Min -- 0.5 x tcyc - 15 0.5 x tcyc - 8 -- -- -- -- 15 0 -- -- -- -- -- Condition B Max 20 -- -- 15 15 15 15 -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 2.0 x tcyc - 20 2.5 x tcyc - 20 3.0 x tcyc - 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 7.6 to 7.10
Read data access time 1 tACC1 Read data access time 2 tACC2 Read data access time 3 tACC3 Read data access time 4 tACC4 Read data access time 5 tACC5
239
Condition A Item WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time BREQO delay time Symbol tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH tBRQS tBACD tBZD tBRQOD Min -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0.5 x tcyc - 20 0.5 x tcyc - 10 30 5 30 -- -- -- Max 20 20 -- -- 30 -- -- -- -- -- 15 50 30 Min -- --
Condition B Max 15 15 -- -- 20 -- -- -- -- -- 15 40 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 7.12 Figure 7.11 Figure 7.8 Test Conditions Figures 7.6 to 7.10
1.0 x tcyc - 15 1.5 x tcyc - 15 -- 0.5 x tcyc - 15 0.5 x tcyc - 8 25 5 30 -- -- --
240
T1 o tAD A23 to A0 tCSD1 CS7 to CS0 tASD AS tRSD1 RD (read) D15 to D0 (read) tWRD2 HWR, LWR (write) tAS tWDD D15 to D0 (write) tACC2 tAS
T2
tAH
tASD
tRSD2
tAS
tACC3
tRDS tRDH
tWRD2
tWSW1
tAH tWDH
Figure 7.6 Basic Bus Timing (2-State Access)
241
T1
T2
T3
o tAD A23 to A0 tCSD1 CS7 to CS0 tASD AS tRSD1 RD (read) D15 to D0 (read) tAS tACC5 tRDS tRDH tACC4 tRSD2 tASD tAS tAH
tWRD1 HWR, LWR (write) D15 to D0 (write)
tWRD2 tAH tWDH
tWDD
tWDS
tWSW2
Figure 7.7 Basic Bus Timing (3-State Access)
242
T1 o
T2
Tw
T3
A23 to A0
CS7 to CS0
AS RD (read) D15 to D0 (read) HWR to LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH
Figure 7.8 Basic Bus Timing (3-State Access, 1 Wait)
243
T1
T2 or T3
T1
T2
o tAD A23 to A0 tAS CS0 tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH tASD tAH
Figure 7.9 Burst ROM Access Timing (2-State Access)
244
T1 o
T2 or T3
T1
tAD A23 to A0
CS0
AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read)
Figure 7.10 Burst ROM Access Timing (1-State Access)
245
o tBRQS BREQ tBACD BACK tBZD tBZD tBACD tBRQS
A23 to A0, CS7 to CS0, AS, RD, HWR, LWR
Figure 7.11 External Bus Release Timing
o tBRQOD BREQO tBRQOD
Figure 7.12 External Bus Request Output Timing
246
(4) Timing of On-Chip Supporting Modules Table 7.7 Timing of On-Chip Supporting Modules
Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item I/O ports Output data delay time Input data setup time Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification 8-bit timer Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification WDT Overflow output delay time Symbol tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL tTMOD tTMRS tTMCS tTMCWH tTMCWL tWOVD Min -- 30 30 -- 30 30 1.5 2.5 -- 30 30 1.5 2.5 -- Max 50 -- -- 50 -- -- -- -- 50 -- -- -- -- 50 Condition B Min -- 25 25 -- 25 25 1.5 2.5 -- 25 25 1.5 2.5 -- Max 40 -- -- 40 -- -- -- -- 40 -- -- -- -- 40 ns Figure 7.19 ns ns ns tcyc Figure 7.16 Figure 7.18 Figure 7.17 ns tcyc Figure 7.15 ns Figure 7.14 Unit ns Test Conditions Figure 7.13
247
Condition A Item SCI Input clock cycle Asynchronous Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS Symbol tScyc Min 4 6 0.4 -- -- -- 50 50 30 Max -- -- 0.6 1.5 1.5 50 -- -- --
Condition B Min 4 6 0.4 -- -- -- 40 40 30 Max -- -- 0.6 1.5 1.5 40 -- -- -- ns ns ns ns tScyc tcyc Unit tcyc
Test Conditions Figure 7.20
Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time
Figure 7.21
Figure 7.22
T1 o tPRS Ports 1 to 4, A to G (read) tPRH
T2
tPWD Ports 1 to 3, A to G (write)
Figure 7.13 I/O Port Input/Output Timing
248
o tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3
Figure 7.14 TPU Input/Output Timing
o tTCKS TCLKA to TCLKD tTCKS
tTCKWL
tTCKWH
Figure 7.15 TPU Clock Input Timing
o tTMOD TMO0, TMO1
Figure 7.16 8-Bit Timer Output Timing
249
o tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS
Figure 7.17 8-Bit Timer Clock Input Timing
o tTMRS TMRI0, TMRI1
Figure 7.18 8-Bit Timer Reset Input Timing
o tWOVD WDTOVF tWOVD
Figure 7.19 WDT Output Timing
tSCKW SCK0, SCK1
tSCKr
tSCKf
tScyc
Figure 7.20 SCK Clock Input Timing
250
SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) tRXS RxD0, RxD1 (receive data) tRXH
Figure 7.21 SCI Input/Output Timing (Synchronous Mode)
o tTRGS ADTRG
Figure 7.22 A/D Converter External Trigger Input Timing
251
7.1.4 Table 7.8
A/D Conversion Characteristics A/D Conversion Characteristics
Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 6.7 -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 5.5 5.5 5.5 0.5 6.0 Min 10 10.6 -- -- -- -- -- -- -- Condition B Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 5.5 5.5 5.5 0.5 6.0 Unit Bits s pF k LSB LSB LSB LSB LSB
252
7.1.5 Table 7.9
D/A Conversion Characteristics D/A Conversion Characteristics
Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Resolution Conversion time Absolute accuracy Min 8 -- -- -- Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Min 8 -- -- -- Condition B Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Unit Bits s LSB LSB 20 pF capacitive load 2 M resistive load 4 M resistive load Test Conditions
253
7.2
Electrical Characteristics of Mask ROM Version (H8S/2318, H8S/2317) in Low-Voltage Operation
Absolute Maximum Ratings
7.2.1
Table 7.10 lists the absolute maximum ratings. Table 7.10 Absolute Maximum Ratings
Item Power supply voltage Input voltage (except port 4) Input voltage (port 4) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Storage temperature Symbol VCC Vin Vin Vr ef AVCC VAN Topr Tstg Value -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.3 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 -55 to +125 Unit V V V V V V C C
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
254
7.2.2
DC Characteristics
Table 7.11 DC Characteristics Condition C: VCC = 2.4 V to 3.6 V, AVCC = 2.4 V to 3.6 V, Vref = 2.4 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications)
Item Schmitt Ports 1, 2, trigger input IRQ0 to IRQ7 voltage Input high voltage Symbol VT - VT
+ + -
Min VCC x 0.2 -- VCC x 0.9 VCC x 0.7 2.2 2.2
Typ -- --
Max -- VCC x 0.7 -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.1 VCC x 0.2 -- -- 0.4 10.0 1.0 1.0 1.0
Unit V V V V V V
Test Conditions
VT - VT VCC x 0.07 -- -- -- -- -- -- -- -- -- -- -- -- -- --
RES, STBY, NMI, VIH MD2 to MD0 EXTAL Ports 3, A to G Port 4
AVCC + 0.3 V V V V V V A A A A Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V I OH = -200 A I OH = -1 mA I OL = 1.6 mA Vin = 0.5 to VCC - 0.5 V
Input low voltage
RES, STBY, MD2 to MD0 NMI, EXTAL, ports 3, 4, A to G
VIL
-0.3 -0.3
Output high All output pins voltage Output low voltage Input leakage current All output pins RES STBY, NMI, MD2 to MD0 Port 4 Three-state Ports 1, 2, 3, A to G leakage current (off state)
VOH
VCC - 0.5 VCC - 1.0
VOL | Iin |
-- -- -- --
| ITSI |
--
255
Item Input pull-up Ports A to E MOS current Input RES capacitance NMI All input pins except RES and NMI Current Normal operation dissipation* 2 Sleep mode Standby mode*
3
Symbol Min -I p Cin 10 -- -- --
Typ -- -- -- --
Max 300 30 30 15
Unit A pF pF pF
Test Conditions Vin = 0V Vin = 0 V f = 1 MHz Ta = 25C
I CC* 4
-- -- -- --
18 (2.7 V) 12 (2.7 V) 0.01 -- 0.2 (3.0 V) 0.01 1.4 (3.0 V) 0.01 --
39 26 10 80 2.0 5.0 3.0 5.0 --
mA mA A
f = 14 MHz f = 14 MHz Ta 50C 50C < Ta
Analog power supply voltage Reference power supply voltage
During A/D and D/A conversion Idle During A/D and D/A conversion Idle
AI CC
-- --
mA A mA A V
AI CC
-- --
RAM standby voltage
VRAM
2.0
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to V CC, and the AVSS pin to VSS . 2. Current dissipation values are for V IH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and all MOS input pull-ups in the off state. 3. The values are for VRAM V CC < 2.4 V, VIH min = VCC x 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 0.74 (mA/(MHz x V)) x V CC x f (normal operation) I CC max = 1.0 (mA) + 0.50 (mA/(MHz x V)) x V CC x f (sleep mode)
256
Table 7.12 Permissible Output Currents Condition C: VCC = 2.4 V to 3.6 V, AVCC = 2.4 V to 3.6 V, Vref = 2.4 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications)
Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins All output pins Total of all output pins Symbol I OL IOL -I OH -IOH Min -- -- -- -- Typ -- -- -- -- Max 2.0 80 2.0 40 Unit mA mA mA mA
Note: To protect chip reliability, do not exceed the output current values in table 7.12.
7.2.3
AC Characteristics
3V
RL Chip output pin C RH C = 50 pF: ports 1, A to F C = 30 pF: ports 2, 3, G RL = 2.4 k RH = 12 k Input/output timing measurement level: 1.5 V (VCC = 2.4 V to 3.6 V)
Figure 7.23 Output Load Circuit
257
(1) Clock Timing Table 7.13 Clock Timing Condition C: VCC = 2.4 V to 3.6 V, AVCC = 2.4 V to 3.6 V, Vref = 2.4 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 14 MHz, Ta = -20C to 75C (regular specifications)
Condition C Item Clock cycle time Clock pulse high width Clock pulse low width Clock rise time Clock fall time Reset oscillation stabilization time (crystal) Software standby oscillation stabilization time (crystal) External clock output stabilization delay time Symbol t cyc t CH t CL t Cr t Cf t OSC1 t OSC2 t DEXT Min 71 28 28 -- -- 10 10 500 Max 500 -- -- 7.5 7.5 -- -- -- Unit ns ns ns ns ns ms ms s Figure 7.3 Figure 7.3 Test Conditions Figure 7.2
258
(2) Control Signal Timing Table 7.14 Control Signal Timing Condition C: VCC = 2.4 V to 3.6 V, AVCC = 2.4 V to 3.6 V, Vref = 2.4 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 14 MHz, Ta = -20C to 75C (regular specifications)
Condition C Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (in recovery from software standby mode) IRQ setup time IRQ hold time IRQ pulse width (in recovery from software standby mode) Symbol t RESS t RESW t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW Min 200 20 150 10 200 150 10 200 Max -- -- -- -- -- -- -- -- ns Unit ns t cyc ns Figure 7.5 Test Conditions Figure 7.4
259
(3) Bus Timing Table 7.15 Bus Timing Condition C: VCC = 2.4 V to 3.6 V, AVCC = 2.4 V to 3.6 V, Vref = 2.4 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 14 MHz, Ta = -20C to 75C (regular specifications)
Condition C Item Address delay time Address setup time Address hold time CS delay time 1 AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time BREQO delay time Symbol t AD t AS t AH t CSD1 t ASD t RSD1 t RSD2 t RDS t RDH t ACC1 t ACC2 t ACC3 t ACC4 t ACC5 t WRD1 t WRD2 t WSW1 t WSW2 t WDD t WDS t WDH t WTS t WTH t BRQS t BACD t BZD t BRQOD Min -- 0.5 x tcyc - 15 0.5 x tcyc - 15 -- -- -- -- 15 0 -- -- -- -- -- -- -- 1.0 x tcyc - 25 1.5 x tcyc - 25 -- 0.5 x tcyc - 25 0.5 x tcyc - 15 40 5 30 -- -- -- Max 20 -- -- 25 25 25 25 -- -- 1.0 x tcyc - 35 1.5 x tcyc - 35 2.0 x tcyc - 35 2.5 x tcyc - 35 3.0 x tcyc - 35 25 25 -- -- 30 -- -- -- -- -- 15 70 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 7.12 Figure 7.11 Figure 7.8 Test Conditions Figures 7.6 to 7.10
260
(4) Timing of On-Chip Supporting Modules Table 7.16 Timing of On-Chip Supporting Modules Condition C: VCC = 2.4 V to 3.6 V, AVCC = 2.4 V to 3.6 V, Vref = 2.4 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 14 MHz, Ta = -20C to 75C (regular specifications)
Condition C Item I/O ports Output data delay time Input data setup time Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification 8-bit timer Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification WDT SCI Overflow output delay time Input clock cycle Asynchronous Synchronous t SCKW t SCKr t SCKf t TXD t RXS t RXH t TRGS Symbol t PWD t PRS t PRH t TOCD t TICS t TCKS t TCKWH t TCKWL t TMOD t TMRS t TMCS t TMCWH t TMCWL t WOVD t Scyc Min -- 40 40 -- 40 40 1.5 2.5 -- 40 40 1.5 2.5 -- 4 6 0.4 -- -- -- 70 70 30 Max 70 -- -- 70 -- -- -- -- 70 -- -- -- -- 70 -- -- 0.6 1.5 1.5 70 -- -- -- ns ns ns ns Figure 7.22 Figure 7.21 t Scyc t cyc ns t cyc Figure 7.19 Figure 7.20 ns ns ns t cyc Figure 7.16 Figure 7.18 Figure 7.17 ns t cyc Figure 7.15 ns Figure 7.14 Unit ns Test Conditions Figure 7.13
Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time
261
7.2.4
A/D Conversion Characteristics
Table 7.17 A/D Conversion Characteristics Condition C: VCC = 2.4 V to 3.6 V, AVCC = 2.4 V to 3.6 V, Vref = 2.4 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 14 MHz, Ta = -20C to 75C (regular specifications)
Condition C Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 19.0 -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 7.5 7.5 7.5 0.5 8.0 Unit Bits s pF k LSB LSB LSB LSB LSB
7.2.5
D/A Conversion Characteristics
Table 7.18 D/A Conversion Characteristics Condition C: VCC = 2.4 V to 3.6 V, AVCC = 2.4 V to 3.6 V, Vref = 2.4 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 14 MHz, Ta = -20C to 75C (regular specifications)
Condition C Item Resolution Conversion time Absolute accuracy Min 8 -- -- -- Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Unit Bits s LSB LSB 20 pF capacitive load 2 M resistive load 4 M resistive load Conditions
262
7.3
7.3.1
Electrical Characteristics of F-ZTAT Version (H8S/2318)
Absolute Maximum Ratings -- Preliminary --
Table 7.19 Absolute Maximum Ratings
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Item Power supply voltage Input voltage (FWE) Input voltage (except port 4) Input voltage (port 4) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC Vin Vin Vin Vr ef AVCC VAN Topr Value -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.3 -0.3 to AVCC +0.3 Regular specifications: -20 to +75* Wide-range specifications: -40 to +85* Storage temperature Tstg -55 to +125 Unit V V V V V V V C C C
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Note: * Condition A (In planning): The operating temperature ranges for flash memory programming/erasing are Ta = 0C to +TBDC (regular specifications) and Ta = 0C to +TBDC (wide-range specifications). The power-supply voltage range for flash memory programming/erasing is VCC = 3.0 V to 3.6 V. Condition B: The operating temperature ranges for flash memory programming/erasing are Ta = 0C to +75C (regular specifications) and Ta = 0C to +85C (widerange specifications).
263
7.3.2
DC Characteristics -- Preliminary --
Table 7.20 (a) DC Characteristics
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Schmitt Ports 1, 2, trigger input IRQ0 to IRQ7 voltage Symbol VT - Min VCC x 0.2 Typ -- Max -- Unit V Test Conditions
VT +
+ -
-- VCC x 0.9 VCC x 0.7 2.2 2.2 -0.3 -0.3
--
VCC x 0.7 -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.1 VCC x 0.2 -- -- 0.4 10.0 1.0 1.0 1.0
V V V V V
VT - VT VCC x 0.07 -- Input high voltage RES, STBY, NMI, VIH MD2 to MD0, FWE EXTAL Ports 3, A to G Port 4 Input low voltage RES, STBY, VIL MD2 to MD0, FWE NMI, EXTAL, ports 3, 4, A to G Output high All output pins voltage Output low voltage Input leakage current All output pins RES STBY, NMI, MD2 to MD0, FWE Port 4 Three-state Ports 1, 2, 3, A to G leakage current (off state) | ITSI | VOH -- -- -- -- -- -- -- -- -- -- -- -- --
AVCC + 0.3 V V V V V V A A A A Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V I OH = -200 A I OH = -1 mA I OL = 1.6 mA Vin = 0.5 to VCC - 0.5 V
VCC - 0.5 VCC - 1.0
VOL | Iin |
-- -- -- -- --
264
Item Input pull-up Ports A to E MOS current Input capacitance RES NMI All input pins except RES and NMI
Symbol -I p
Min 10
Typ --
Max 300
Unit A
Test Conditions VCC = 2.7 V to 3.6 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C
Cin
-- -- --
-- -- --
30 30 15
pF pF pF
Current Normal operation I CC* 4 2 dissipation* Sleep mode Standby mode*
3
--
35 (3.0 V) 25 (3.0 V)
80 64 10 80 2.0 5.0 3.0 5.0 --
mA mA A
f = 20 MHz f = 20 MHz Ta 50C 50C < Ta
-- --
0.01 -- 0.2 (3.0 V) 0.01 1.4 (3.0 V) 0.01 --
Analog power supply voltage Reference power supply voltage
During A/D and D/A conversion Idle During A/D and D/A conversion Idle
AI CC
-- --
mA A mA A V
AI CC
-- --
RAM standby voltage
VRAM
2.0
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to V CC, and the AVSS pin to VSS . 2. Current dissipation values are for V IH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and all MOS input pull-ups in the off state. 3. The values are for VRAM V CC < 2.7 V, VIH min = VCC x 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 1.10 (mA/(MHz x V)) x V CC x f (normal operation) I CC max = 1.0 (mA) + 0.88 (mA/(MHz x V)) x V CC x f (sleep mode)
265
Table 7.20 (b) DC Characteristics
-- Preliminary --
Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Schmitt Ports 1, 2, trigger input IRQ0 to IRQ7 voltage Symbol VT - Min VCC x 0.2 Typ -- Max -- Unit V Test Conditions
VT +
+ -
-- VCC x 0.9 VCC x 0.7 2.2 2.2 -0.3 -0.3
--
VCC x 0.7 -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.1 VCC x 0.2 -- -- 0.4 10.0 1.0 1.0 1.0
V V V V V
VT - VT VCC x 0.07 -- Input high voltage RES, STBY, NMI, VIH MD2 to MD0, FWE EXTAL Ports 3, A to G Port 4 Input low voltage RES, STBY, VIL MD2 to MD0, FWE NMI, EXTAL, ports 3, 4, A to G Output high All output pins voltage Output low voltage Input leakage current All output pins RES STBY, NMI, MD2 to MD0, FWE Port 4 Three-state Ports 1, 2, 3, A to G leakage current (off state) | ITSI | VOH -- -- -- -- -- -- -- -- -- -- -- -- --
AVCC + 0.3 V V V V V V A A A A Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V I OH = -200 A I OH = -1 mA I OL = 1.6 mA Vin = 0.5 to VCC - 0.5 V
VCC - 0.5 VCC - 1.0
VOL | Iin |
-- -- -- -- --
266
Item Input pull-up Ports A to E MOS current Input capacitance RES NMI All input pins except RES and NMI
Symbol -I p
Min 10
Typ --
Max 300
Unit A
Test Conditions VCC = 3.0 V to 3.6 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C
Cin
-- -- --
-- -- --
30 30 15
pF pF pF
Current Normal operation I CC* 4 2 dissipation* Sleep mode Standby mode*
3
--
50 (3.3 V) 35 (3.3 V)
100 80 10 80 2.0 5.0 3.0 5.0 --
mA mA A
f = 25 MHz f = 25 MHz Ta 50C 50C < Ta
-- --
0.01 -- 0.2 (3.0 V) 0.01 1.4 (3.0 V) 0.01 --
Analog power supply voltage Reference power supply voltage
During A/D and D/A conversion Idle During A/D and D/A conversion Idle
AI CC
-- --
mA A mA A V
AI CC
-- --
RAM standby voltage
VRAM
2.0
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to V CC, and the AVSS pin to VSS . 2. Current dissipation values are for V IH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and all MOS input pull-ups in the off state. 3. The values are for VRAM V CC < 3.0 V, VIH min = VCC x 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 1.10 (mA/(MHz x V)) x V CC x f (normal operation) I CC max = 1.0 (mA) + 0.88 (mA/(MHz x V)) x V CC x f (sleep mode)
267
Table 7.21 (a) Permissible Output Currents
-- Preliminary --
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications)
Item Permissible output low All output pins current (per pin) Permissible output low Total of all output current (total) pins Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins Symbol I OL IOL -I OH -IOH Min -- -- -- -- Typ -- -- -- -- Max 2.0 80 2.0 40 Unit mA mA mA mA
Note: To protect chip reliability, do not exceed the output current values in table 7.12 (a).
Table 7.21 (b) Permissible Output Currents Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications)
Item Permissible output low All output pins current (per pin) Permissible output low Total of all output current (total) pins Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins Symbol I OL IOL -I OH -IOH Min -- -- -- -- Typ -- -- -- --
-- Preliminary --
Max 2.0 80 2.0 40
Unit mA mA mA mA
Note: To protect chip reliability, do not exceed the output current values in table 7.12 (b).
268
7.3.3
AC Characteristics
(1) Clock Timing Table 7.22 Clock Timing -- Preliminary --
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Clock cycle time Clock pulse high width Clock pulse low width Clock rise time Clock fall time Reset oscillation stabilization time (crystal) Software standby oscillation stabilization time (crystal) External clock output stabilization delay time Symbol t cyc t CH t CL t Cr t Cf t OSC1 t OSC2 t DEXT Min 50 20 20 -- -- 10 10 500 Max 500 -- -- 5 5 -- -- -- Condition B Min 40 15 15 -- -- 10 10 500 Max 500 -- -- 5 5 -- -- -- Unit ns ns ns ns ns ms ms s Figure 7.3 Figure 7.3 Test Conditions Figure 7.2
269
(2) Control Signal Timing Table 7.23 Control Signal Timing -- Preliminary --
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (in recovery from software standby mode) IRQ setup time IRQ hold time IRQ pulse width (in recovery from software standby mode) Symbol t RESS t RESW t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW Min 200 20 150 10 200 150 10 200 Max -- -- -- -- -- -- -- -- Condition B Min 200 20 150 10 200 150 10 200 Max -- -- -- -- -- -- -- -- ns Unit ns t cyc ns Figure 7.5 Test Conditions Figure 7.4
270
(3) Bus Timing Table 7.24 Bus Timing -- Preliminary --
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Address delay time Address setup time Address hold time CS delay time 1 AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Symbol tAD tAS tAH tCSD1 tASD tRSD1 tRSD2 tRDS tRDH Min -- 0.5 x tcyc - 15 0.5 x tcyc - 10 -- -- -- -- 15 0 -- -- -- -- -- Max 20 -- -- 20 20 20 20 -- -- 1.0 x tcyc - 25 1.5 x tcyc - 25 2.0 x tcyc - 25 2.5 x tcyc - 25 3.0 x tcyc - 25 Min -- 0.5 x tcyc - 15 0.5 x tcyc - 8 -- -- -- -- 15 0 -- -- -- -- -- Condition B Max 20 -- -- 15 15 15 15 -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 2.0 x tcyc - 20 2.5 x tcyc - 20 3.0 x tcyc - 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 7.6 to 7.10
Read data access time 1 tACC1 Read data access time 2 tACC2 Read data access time 3 tACC3 Read data access time 4 tACC4 Read data access time 5 tACC5
271
Condition A Item WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time BREQO delay time Symbol tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH tBRQS tBACD tBZD tBRQOD Min -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0.5 x tcyc - 20 0.5 x tcyc - 10 30 5 30 -- -- -- Max 20 20 -- -- 30 -- -- -- -- -- 15 50 30 Min -- --
Condition B Max 15 15 -- -- 20 -- -- -- -- -- 15 40 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 7.12 Figure 7.11 Figure 7.8 Test Conditions Figures 7.6 to 7.10
1.0 x tcyc - 15 1.5 x tcyc - 15 -- 0.5 x tcyc - 15 0.5 x tcyc - 8 25 5 30 -- -- --
272
(4) Timing of On-Chip Supporting Modules Table 7.25 Timing of On-Chip Supporting Modules --Preliminary--
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item I/O ports Output data delay time Input data setup time Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification 8-bit timer Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification Symbol tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL tTMOD tTMRS tTMCS tTMCWH tTMCWL Min -- 30 30 -- 30 30 1.5 2.5 -- 30 30 1.5 2.5 Max 50 -- -- 50 -- -- -- -- 50 -- -- -- -- Condition B Min -- 25 25 -- 25 25 1.5 2.5 -- 25 25 1.5 2.5 Max 40 -- -- 40 -- -- -- -- 40 -- -- -- -- ns ns ns tcyc Figure 7.16 Figure 7.18 Figure 7.17 ns tcyc Figure 7.15 ns Figure 7.14 Unit ns Test Conditions Figure 7.13
273
Condition A Item SCI Input clock cycle Asynchronous Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS Symbol tScyc Min 4 6 0.4 -- -- -- 50 50 30 Max -- -- 0.6 1.5 1.5 50 -- -- --
Condition B Min 4 6 0.4 -- -- -- 40 40 30 Max -- -- 0.6 1.5 1.5 40 -- -- -- ns ns ns ns tScyc tcyc Unit tcyc
Test Conditions Figure 7.20
Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time
Figure 7.21
Figure 7.22
274
7.3.4
A/D Conversion Characteristics -- Preliminary --
Table 7.26 A/D Conversion Characteristics
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 6.7 -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 5.5 5.5 5.5 0.5 6.0 Min 10 10.6 -- -- -- -- -- -- -- Condition B Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 5.5 5.5 5.5 0.5 6.0 Unit Bits s pF k LSB LSB LSB LSB LSB
275
7.3.5
D/A Conversion Characteristics -- Preliminary --
Table 7.27 D/A Conversion Characteristics
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, Ta = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Resolution Conversion time Absolute accuracy Min 8 -- -- -- Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Min 8 -- -- -- Condition B Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Unit Bits s LSB LSB 20 pF capacitive load 2 M resistive load 4 M resistive load Test Conditions
276
7.3.6
Flash Memory Characteristics -- Preliminary --
Table 7.28 (a) Flash Memory Characteristics
Condition A*7 (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, (program/erase power-supply voltage range: VCC = 3.0 V to 3.6 V), Ta = 0C to +75C (program/erase operating temperature range: regular specifications), Ta = 0C to +85C (program/erase operating temperature range: wide-range specifications)
Item Programming time*1, *2, *4 Erase time*1, *3, *6 Rewrite times Programming Wait time after SWE bit setting*1 Wait time after PSU bit setting*
1
Symbol tP tE NWEC x y z (z1) (z2) (z3)
Min -- -- -- 1 50 -- -- --
Typ TBD TBD -- -- -- -- -- --
Max 200 1000 TBD -- -- 30 200 10
Unit ms/ 128 bytes ms/block Times s s s s s
Test Conditions
Wait time after P bit setting*1, *4
1n6 7 n 1000
Additionalprogramming time wait
Wait time after P bit clearing*1 Wait time after PSU bit clearing* Wait time after PV bit setting*1 Wait time after H'FF dummy write* Wait time after PV bit clearing*1 Wait time after SWE bit clearing* Maximum number of writes*1, *4 Erasing Wait time after SWE bit setting*1 Wait time after ESU bit setting*1 Wait time after E bit setting* * Wait time after E bit clearing*1 Wait time after ESU bit clearing* Wait time after EV bit setting*1 Wait time after H'FF dummy write* Wait time after EV bit clearing*1 Wait time after SWE bit clearing* Maximum number of erases*1, *6
1 1 1 1, 6 1 1 1
N x y z N
5 5 4 2 2 100 -- 1 100 -- 10 10 20 2 4 100 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- --
s s s s s s s s s s s s s s s Times
1000*5 Times -- -- 10 -- -- -- -- -- -- 100
277
Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1. Does not include the erase-verify time.) 4. Maximum programming time
tP(max) =
i=1
wait time after P bit setting (z)
N
5. The maximum number of writes (N) should be set as shown below according to the actual set value of z so as not to exceed the maximum programming time (t P(max)). The wait time after P bit setting (z) should be changed as follows according to the number of writes (n). Number of writes (n) 1n6 z = 30 s 7 n 1000 z = 200 s [In additional programming] Number of writes (n) 1n6 z = 10 s 6. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (z) and the maximum number of erases (N): t E(max) = Wait time after E bit setting (z) x maximum number of erases (N) 7. The power-supply voltage range for flash memory programming/erasing is VCC = 3.0 V to 3.6 V.
278
Table 7.28 (b) Flash Memory Characteristics
-- Preliminary --
Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = 0C to +75C (program/erase operating temperature range: regular specifications), Ta = 0C to +85C (program/erase operating temperature range: wide-range specifications)
Item Programming time*1, *2, *4 Erase time*1, *3, *6 Rewrite times Programming Wait time after SWE bit setting*
1, 1
Symbol tP tE NWEC x y z (z1) (z2) (z3) Wait time after PSU bit setting*1 Wait time after P bit setting* *
4
Min -- -- -- 1 50 -- -- --
Typ 10 50 -- -- -- -- -- --
Max 200 1000 100 -- -- 30 200 10
Unit ms/ 128 bytes ms/block Times s s s s s
Test Conditions
1n6 7 n 1000
Additionalprogramming time wait
Wait time after P bit clearing*1 Wait time after PSU bit clearing*1 Wait time after PV bit setting*
1
N x y z N
6 1 1
5 5 4 2 2 100 -- 1 100 -- 10 10 20 2 4 100 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- --
5
s s s s s s s s s s s s s s s Times
Wait time after H'FF dummy write*1 Wait time after PV bit clearing*
1,
Wait time after SWE bit clearing*1 Maximum number of writes* * Erasing
4
1000* Times -- -- 10 -- -- -- -- -- -- 100
Wait time after SWE bit setting*1 Wait time after ESU bit setting*
1 1
Wait time after E bit setting*1, *6 Wait time after E bit clearing* Wait time after ESU bit clearing*1 Wait time after EV bit setting*
1
Wait time after H'FF dummy write*1 Wait time after EV bit clearing*
1,
Wait time after SWE bit clearing*1 Maximum number of erases* *
Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1. Does not include the erase-verify time.) 279
4. Maximum programming time
tP(max) =
i=1
wait time after P bit setting (z)
N
5. The maximum number of writes (N) should be set as shown below according to the actual set value of z so as not to exceed the maximum programming time (t P(max)). The wait time after P bit setting (z) should be changed as follows according to the number of writes (n). Number of writes (n) 1n6 z = 30 s 7 n 1000 z = 200 s [In additional programming] Number of writes (n) 1n6 z = 10 s 6. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (z) and the maximum number of erases (N): t E(max) = Wait time after E bit setting (z) x maximum number of erases (N) 7. The power-supply voltage range for flash memory programming/erasing is VCC = 3.0 V to 3.6 V.
280
7.4
Electrical Characteristics of F-ZTAT Version (H8S/2315) (Under Development)
Absolute Maximum Ratings -- Preliminary --
Value -0.3 to +4.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.3 -0.3 to AVCC +0.3 Regular specifications: -20 to +75* Wide-range specifications: -40 to +85* Unit V V V V V V V C C C
7.4.1
Table 7.29 Absolute Maximum Ratings
Item Power supply voltage Input voltage (FWE) Input voltage (except port 4) Input voltage (port 4) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC Vin Vin Vin Vr ef AVCC VAN Topr
Storage temperature
Tstg
-55 to +125
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Note: * The operating temperature ranges for flash memory programming/erasing are as follows: Ta = 0C to +TBDC (regular specifications), Ta = 0C to +TBDC (wide-range specifications). The power-supply voltage range for flash memory programming/erasing is VCC = 3.0 V to 3.6 V.
281
7.4.2
DC Characteristics -- Preliminary --
Table 7.30 (a) DC Characteristics
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Schmitt Ports 1, 2, trigger input IRQ0 to IRQ7 voltage Symbol VT - Min VCC x 0.2 Typ -- Max -- Unit V Test Conditions
VT +
+ -
-- VCC x 0.9 VCC x 0.7 2.2 2.2 -0.3 -0.3
--
VCC x 0.7 -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.1 VCC x 0.2 -- -- 0.4 10.0 1.0 1.0 1.0
V V V V V
VT - VT VCC x 0.07 -- Input high voltage RES, STBY, NMI, VIH MD2 to MD0, FWE EXTAL Ports 3, A to G Port 4 Input low voltage RES, STBY, VIL MD2 to MD0, FWE NMI, EXTAL, ports 3, 4, A to G Output high All output pins voltage Output low voltage Input leakage current All output pins RES STBY, NMI, MD2 to MD0, FWE Port 4 Three-state Ports 1, 2, 3, A to G leakage current (off state) | ITSI | VOH -- -- -- -- -- -- -- -- -- -- -- -- --
AVCC + 0.3 V V V V V V A A A A Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V I OH = -200 A I OH = -1 mA I OL = 1.6 mA Vin = 0.5 to VCC - 0.5 V
VCC - 0.5 VCC - 1.0
VOL | Iin |
-- -- -- -- --
282
Item Input pull-up Ports A to E MOS current Input capacitance RES NMI All input pins except RES and NMI
Symbol -I p
Min 10
Typ --
Max 300
Unit A
Test Conditions VCC = 2.7 V to 3.6 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C
Cin
-- -- --
-- -- --
30 30 15
pF pF pF
Current Normal operation I CC* 4 2 dissipation* Sleep mode Standby mode*
3
--
TBD (3.0 V) TBD TBD (3.0 V) TBD
mA mA A
f = 20 MHz f = 20 MHz Ta 50C 50C < Ta
-- --
0.01 -- 0.2 (3.0 V) 0.01 1.4 (3.0 V) 0.01 --
10 80 2.0 5.0 3.0 5.0 --
Analog power supply voltage Reference power supply voltage
During A/D and D/A conversion Idle During A/D and D/A conversion Idle
AI CC
-- --
mA A mA A V
AI CC
-- --
RAM standby voltage
VRAM
2.0
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to V CC, and the AVSS pin to VSS . 2. Current dissipation values are for V IH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and all MOS input pull-ups in the off state. 3. The values are for VRAM V CC < 2.7 V, VIH min = VCC x 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + TBD (mA/(MHz x V)) x V CC x f (normal operation) I CC max = 1.0 (mA) + TBD (mA/(MHz x V)) x V CC x f (sleep mode)
283
Table 7.30 (b) DC Characteristics
-- Preliminary --
Condition B (Under development): VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Schmitt Ports 1, 2, trigger input IRQ0 to IRQ7 voltage Symbol VT - Min VCC x 0.2 Typ -- Max -- Unit V Test Conditions
VT +
+ -
-- VCC x 0.9 VCC x 0.7 2.2 2.2 -0.3 -0.3
--
VCC x 0.7 -- VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC x 0.1 VCC x 0.2 -- -- 0.4 10.0 1.0 1.0 1.0
V V V V V
VT - VT VCC x 0.07 -- Input high voltage RES, STBY, NMI, VIH MD2 to MD0, FWE EXTAL Ports 3, A to G Port 4 Input low voltage RES, STBY, VIL MD2 to MD0, FWE NMI, EXTAL, ports 3, 4, A to G Output high All output pins voltage Output low voltage Input leakage current All output pins RES STBY, NMI, MD2 to MD0, FWE Port 4 Three-state Ports 1, 2, 3, A to G leakage current (off state) | ITSI | VOH -- -- -- -- -- -- -- -- -- -- -- -- --
AVCC + 0.3 V V V V V V A A A A Vin = 0.5 to AVCC - 0.5 V Vin = 0.5 to VCC - 0.5 V I OH = -200 A I OH = -1 mA I OL = 1.6 mA Vin = 0.5 to VCC - 0.5 V
VCC - 0.5 VCC - 1.0
VOL | Iin |
-- -- -- -- --
284
Item Input pull-up Ports A to E MOS current Input capacitance RES NMI All input pins except RES and NMI
Symbol -I p
Min 10
Typ --
Max 300
Unit A
Test Conditions VCC = 3.0 V to 3.6 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C
Cin
-- -- --
-- -- --
30 30 15
pF pF pF
Current Normal operation I CC* 4 2 dissipation* Sleep mode Standby mode*
3
--
TBD (3.3 V) TBD TBD (3.3 V) TBD
mA mA A
f = 25 MHz f = 25 MHz Ta 50C 50C < Ta
-- --
0.01 -- 0.2 (3.0 V) 0.01 1.4 (3.0 V) 0.01 --
10 80 2.0 5.0 3.0 5.0 --
Analog power supply voltage Reference power supply voltage
During A/D and D/A conversion Idle During A/D and D/A conversion Idle
AI CC
-- --
mA A mA A V
AI CC
-- --
RAM standby voltage
VRAM
2.0
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to V CC, and the AVSS pin to VSS . 2. Current dissipation values are for V IH min = VCC - 0.2 V and VIL max = 0.2 V with all output pins unloaded and all MOS input pull-ups in the off state. 3. The values are for VRAM V CC < 3.0 V, VIH min = VCC x 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + TBD (mA/(MHz x V)) x V CC x f (normal operation) I CC max = 1.0 (mA) + TBD (mA/(MHz x V)) x V CC x f (sleep mode)
285
Table 7.31 (a) Permissible Output Currents Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications)
Item Permissible output low All output pins current (per pin) Permissible output low Total of all output current (total) pins Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins Symbol I OL IOL -I OH -IOH Min -- -- -- -- Typ -- -- -- --
-- Preliminary --
Max 2.0 80 2.0 40
Unit mA mA mA mA
Note: To protect chip reliability, do not exceed the output current values in table 7.31 (a).
Table 7.31 (b) Permissible Output Currents Condition B (Under development): VCC = 3.0 V to 3.6 V, AVCC = 3.0 to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications)
Item Permissible output low All output pins current (per pin) Permissible output low Total of all output current (total) pins Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins Symbol I OL IOL -I OH -IOH Min -- -- -- -- Typ -- -- -- --
-- Preliminary --
Max 2.0 80 2.0 40
Unit mA mA mA mA
Note: To protect chip reliability, do not exceed the output current values in table 7.31 (b).
286
7.4.3
AC Characteristics
(1) Clock Timing Table 7.32 Clock Timing -- Preliminary --
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B (Under development): VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Clock cycle time Clock pulse high width Clock pulse low width Clock rise time Clock fall time Reset oscillation stabilization time (crystal) Software standby oscillation stabilization time (crystal) External clock output stabilization delay time Symbol t cyc t CH t CL t Cr t Cf t OSC1 t OSC2 t DEXT Min 50 20 20 -- -- 10 10 500 Max 500 -- -- 5 5 -- -- -- Condition B Min 40 15 15 -- -- 10 10 500 Max 500 -- -- 5 5 -- -- -- Unit ns ns ns ns ns ms ms s Figure 7.3 Figure 7.3 Test Conditions Figure 7.2
287
(2) Control Signal Timing Table 7.33 Control Signal Timing -- Preliminary --
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B (Under development): VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (in recovery from software standby mode) IRQ setup time IRQ hold time IRQ pulse width (in recovery from software standby mode) Symbol t RESS t RESW t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW Min 200 20 150 10 200 150 10 200 Max -- -- -- -- -- -- -- -- Condition B Min 200 20 150 10 200 150 10 200 Max -- -- -- -- -- -- -- -- ns Unit ns t cyc ns Figure 7.5 Test Conditions Figure 7.4
288
(3) Bus Timing Table 7.34 Bus Timing -- Preliminary --
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B (Under development): VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Address delay time Address setup time Address hold time CS delay time 1 AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Symbol tAD tAS tAH tCSD1 tASD tRSD1 tRSD2 tRDS tRDH Min -- 0.5 x tcyc - 15 0.5 x tcyc - 10 -- -- -- -- 15 0 -- -- -- -- -- Max 20 -- -- 20 20 20 20 -- -- 1.0 x tcyc - 25 1.5 x tcyc - 25 2.0 x tcyc - 25 2.5 x tcyc - 25 3.0 x tcyc - 25 Min -- 0.5 x tcyc - 15 0.5 x tcyc - 8 -- -- -- -- 15 0 -- -- -- -- -- Condition B Max 20 -- -- 15 15 15 15 -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 2.0 x tcyc - 20 2.5 x tcyc - 20 3.0 x tcyc - 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figures 7.6 to 7.10
Read data access time 1 tACC1 Read data access time 2 tACC2 Read data access time 3 tACC3 Read data access time 4 tACC4 Read data access time 5 tACC5
289
Condition A Item WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time BREQO delay time Symbol tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH tWTS tWTH tBRQS tBACD tBZD tBRQOD Min -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0.5 x tcyc - 20 0.5 x tcyc - 10 30 5 30 -- -- -- Max 20 20 -- -- 30 -- -- -- -- -- 15 50 30 Min -- --
Condition B Max 15 15 -- -- 20 -- -- -- -- -- 15 40 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 7.12 Figure 7.11 Figure 7.8 Test Conditions Figures 7.6 to 7.10
1.0 x tcyc - 15 1.5 x tcyc - 15 -- 0.5 x tcyc - 15 0.5 x tcyc - 8 25 5 30 -- -- --
290
(4) Timing of On-Chip Supporting Modules Table 7.35 Timing of On-Chip Supporting Modules --Preliminary--
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B (Under development): VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item I/O ports Output data delay time Input data setup time Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification 8-bit timer Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single-edge specification Both-edge specification Symbol tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL tTMOD tTMRS tTMCS tTMCWH tTMCWL Min -- 30 30 -- 30 30 1.5 2.5 -- 30 30 1.5 2.5 Max 50 -- -- 50 -- -- -- -- 50 -- -- -- -- Condition B Min -- 25 25 -- 25 25 1.5 2.5 -- 25 25 1.5 2.5 Max 40 -- -- 40 -- -- -- -- 40 -- -- -- -- ns ns ns tcyc Figure 7.16 Figure 7.18 Figure 7.17 ns tcyc Figure 7.15 ns Figure 7.14 Unit ns Test Conditions Figure 7.13
291
Condition A Item SCI Input clock cycle Asynchronous Synchronous tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS Symbol tScyc Min 4 6 0.4 -- -- -- 50 50 30 Max -- -- 0.6 1.5 1.5 50 -- -- --
Condition B Min 4 6 0.4 -- -- -- 40 40 30 Max -- -- 0.6 1.5 1.5 40 -- -- -- ns ns ns ns tScyc tcyc Unit tcyc
Test Conditions Figure 7.20
Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D converter Trigger input setup time
Figure 7.21
Figure 7.22
292
7.4.4
A/D Conversion Characteristics -- Preliminary --
Table 7.36 A/D Conversion Characteristics
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B (Under development): VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 6.7 -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 5.5 5.5 5.5 0.5 6.0 Min 10 10.6 -- -- -- -- -- -- -- Condition B Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 5.5 5.5 5.5 0.5 6.0 Unit Bits s pF k LSB LSB LSB LSB LSB
293
7.4.5
D/A Conversion Characteristics -- Preliminary --
Table 7.37 D/A Conversion Characteristics
Condition A (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 20 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications) Condition B (Under development): VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2 MHz to 25 MHz, T a = -20C to 75C (regular specifications), Ta = -40C to 85C (wide-range specifications)
Condition A Item Resolution Conversion time Absolute accuracy Min 8 -- -- -- Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Min 8 -- -- -- Condition B Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Unit Bits s LSB LSB 20 pF capacitive load 2 M resistive load 4 M resistive load Test Conditions
294
7.4.6
Flash Memory Characteristics -- Preliminary --
Table 7.38 (a) Flash Memory Characteristics
Condition A*7 (In planning): VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, (program/erase power-supply voltage range: VCC = 3.0 V to 3.6 V), Ta = 0C to +75C (program/erase operating temperature range: regular specifications), Ta = 0C to +85C (program/erase operating temperature range: wide-range specifications)
Item Programming time*1, *2, *4 Erase time*1, *3, *6 Rewrite times Programming Wait time after SWE bit setting*1 Wait time after PSU bit setting*
1
Symbol tP tE NWEC x y z (z1) (z2) (z3)
Min -- -- -- 1 50 -- -- --
Typ TBD TBD -- -- -- -- -- --
Max 200 1000 TBD -- -- 30 200 10
Unit ms/ 128 bytes ms/block Times s s s s s
Test Conditions
Wait time after P bit setting*1, *4
1n6 7 n 1000
Additionalprogramming time wait
Wait time after P bit clearing*1 Wait time after PSU bit clearing* Wait time after PV bit setting*1 Wait time after H'FF dummy write* Wait time after PV bit clearing*1 Wait time after SWE bit clearing* Maximum number of writes*1, *4 Erasing Wait time after SWE bit setting*1 Wait time after ESU bit setting*1 Wait time after E bit setting* * Wait time after E bit clearing*1 Wait time after ESU bit clearing* Wait time after EV bit setting*1 Wait time after H'FF dummy write* Wait time after EV bit clearing*1 Wait time after SWE bit clearing* Maximum number of erases*1, *6
1 1 1 1, 6 1 1 1
N x y z N
5 5 4 2 2 100 -- 1 100 -- 10 10 20 2 4 100 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- --
s s s s s s s s s s s s s s s Times
1000*5 Times -- -- 10 -- -- -- -- -- -- 100
295
Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1. Does not include the erase-verify time.) 4. Maximum programming time
tP(max) =
i=1
wait time after P bit setting (z)
N
5. The maximum number of writes (N) should be set as shown below according to the actual set value of z so as not to exceed the maximum programming time (t P(max)). The wait time after P bit setting (z) should be changed as follows according to the number of writes (n). Number of writes (n) 1n6 z = 30 s 7 n 1000 z = 200 s [In additional programming] Number of writes (n) 1n6 z = 10 s 6. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (z) and the maximum number of erases (N): t E(max) = Wait time after E bit setting (z) x maximum number of erases (N) 7. The power-supply voltage range for flash memory programming/erasing is V CC = 3.0 V to 3.6 V.
296
Table 7.38 (b) Flash Memory Characteristics
-- Preliminary --
Condition B (Under development): VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = 0C to +75C (program/erase operating temperature range: regular specifications), Ta = 0C to +85C (program/erase operating temperature range: widerange specifications)
Item Programming time*1, *2, *4 Erase time*1, *3, *6 Rewrite times Programming Wait time after SWE bit setting*
1, 1
Symbol tP tE NWEC x y z (z1) (z2) (z3) Wait time after PSU bit setting*1 Wait time after P bit setting* *
4
Min -- -- -- 1 50 -- -- --
Typ TBD TBD -- -- -- -- -- --
Max 200 1000 TBD -- -- 30 200 10
Unit ms/ 128 bytes ms/block Times s s s s s
Test Conditions
1n6 7 n 1000
Additionalprogramming time wait
Wait time after P bit clearing*1 Wait time after PSU bit clearing*1 Wait time after PV bit setting*
1
N x y z N
6 1 1
5 5 4 2 2 100 -- 1 100 -- 10 10 20 2 4 100 --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- --
5
s s s s s s s s s s s s s s s Times
Wait time after H'FF dummy write*1 Wait time after PV bit clearing*
1,
Wait time after SWE bit clearing*1 Maximum number of writes* * Erasing
4
1000* Times -- -- 10 -- -- -- -- -- -- 100
Wait time after SWE bit setting*1 Wait time after ESU bit setting*
1 1
Wait time after E bit setting*1, *6 Wait time after E bit clearing* Wait time after ESU bit clearing*1 Wait time after EV bit setting*
1
Wait time after H'FF dummy write*1 Wait time after EV bit clearing*
1,
Wait time after SWE bit clearing*1 Maximum number of erases* *
Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). Does not include the program-verify time.) 297
3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1. Does not include the erase-verify time.) 4. Maximum programming time
tP(max) =
i=1
wait time after P bit setting (z)
N
5. The maximum number of writes (N) should be set as shown below according to the actual set value of z so as not to exceed the maximum programming time (t P(max)). The wait time after P bit setting (z) should be changed as follows according to the number of writes (n). Number of writes (n) 1n6 z = 30 s 7 n 1000 z = 200 s [In additional programming] Number of writes (n) 1n6 z = 10 s 6. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (z) and the maximum number of erases (N): t E(max) = Wait time after E bit setting (z) x maximum number of erases (N) 7. The power-supply voltage range for flash memory programming/erasing is VCC = 3.0 V to 3.6 V.
7.5
Usage Note
Although both the F-ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip ROM, and the layout patterns. If the F-ZTAT version is used to carry out system evaluation and testing, therefore, when switching to the mask ROM version the same evaluation and testing procedures should also be conducted on this version.
298
Section 8 Registers
8.1 List of Registers (Address Order)
Register Address Name H'F800 to H'FBFF MRA SAR Bit 7 SM1 Bit 6 SM0 Bit 5 DM1 Bit 4 DM0 Bit 3 MD1 Bit 2 MD0 Bit 1 DTS Bit 0 Sz Module Name DTC Data Bus Width 16/32* 1 bits
MRB DAR
CHNE
DISEL
CHNS
--
--
--
--
--
CRA
CRB
H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8B H'FE8C H'FE8D H'FE8E H'FE8F
TCR3 TMDR3 TIOR3H TIOR3L TIER3 TSR3 TCNT3
CCLR2 -- IOB3 IOD3 TTGE --
CCLR1 -- IOB2 IOD2 -- --
CCLR0 BFB IOB1 IOD1 -- --
CKEG1 CKEG0 TPSC2 BFA IOB0 IOD0 TCIEV TCFV MD3 IOA3 IOC3 TGIED TGFD MD2 IOA2 IOC2 TGIEC TGFC
TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
TPSC0 MD0 IOA0 IOC0 TGIEA TGFA
TPU3
16 bits
TGR3A
TGR3B
TGR3C
TGR3D
299
Register Address Name H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 H'FE99 H'FE9A H'FE9B H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB H'FEB0 H'FEB1 H'FEB2 H'FEB9 H'FEBA H'FEBB P1DDR P2DDR P3DDR PADDR PBDDR PCDDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Ports P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR -- -- -- -- P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR -- -- PA3DDR PA2DDR PA1DDR PA0DDR TGR5B TGR5A TCR5 TMDR5 TIOR5 TIER5 TSR5 TCNT5 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 CKEG0 TPSC2 -- IOB0 TCIEV TCFV MD3 IOA3 -- -- MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU5 TGR4B TGR4A TCR4 TMDR4 TIOR4 TIER4 TSR4 TCNT4 Bit 7 -- -- IOB3 TTGE TCFD Bit 6 CCLR1 -- IOB2 -- -- Bit 5 CCLR0 -- IOB1 TCIEU TCFU Bit 4 CKEG -- IOB0 TCIEV TCFV Bit 3 Bit 2 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Module Name TPU4
Data Bus Width 16 bits
CKEG0 TPSC2 MD3 IOA3 -- -- MD2 IOA2 -- --
16 bits
8 bits
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR -- -- -- PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
H'FEBC PDDDR H'FEBD PEDDR H'FEBE H'FEBF PFDDR PGDDR
300
Register Address Name H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 IPRA IPRB IPRC IPRD IPRE IPRF Bit 7 -- -- -- -- -- -- -- -- -- -- -- ABW7 AST7 W71 W31 ICIS1 BRLE
2
Data Bus Bit 6 IPR6 IPR6 IPR6 IPR6 -- IPR6 IPR6 IPR6 IPR6 -- IPR6 ABW6 AST6 W70 W30 ICIS0 Bit 5 IPR5 IPR5 IPR5 IPR5 -- IPR5 IPR5 IPR5 IPR5 -- IPR5 ABW5 AST5 W61 W21 Bit 4 IPR4 IPR4 IPR4 IPR4 -- IPR4 IPR4 IPR4 IPR4 -- IPR4 ABW4 AST4 W60 W20 Bit 3 -- -- -- -- -- -- -- -- -- -- -- ABW3 AST3 W51 W11 Bit 2 IPR2 IPR2 IPR2 -- IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 -- ABW2 AST2 W50 W10 Bit 1 IPR1 IPR1 IPR1 -- IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 -- ABW1 AST1 W41 W01 -- -- RAM1 Bit 0 IPR0 IPR0 IPR0 -- IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 -- ABW0 AST0 W40 W00 -- WAITE RAM0 Flash memory 8 bits 8 bits Bus controller 8 bits Module Name Interrupt controller Width 8 bits
H'FECA IPRG H'FECB IPRH H'FECC IPRI H'FECD IPRJ H'FECE IPRK H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 ABWCR ASTCR WCRH WCRL BCRH BCRL
BRSTRM BRSTS1 BRSTS0 -- -- -- -- RAMS -- RAM2
BREQOE EAE -- --
H'FEDB RAMER* -- H'FF2C H'FF2D H'FF2E H'FF2F H'FF30 to H'FF34 H'FF37 H'FF38 ISCRH ISCRL IER ISR DTCER
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Interrupt IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
controller
IRQ7E IRQ7F
IRQ6E IRQ6F
IRQ5E IRQ5F DTCE5
IRQ4E IRQ4F DTCE4
IRQ3E IRQ3F DTCE3
IRQ2E IRQ2F DTCE2
IRQ1E IRQ1F DTCE1
IRQ0E IRQ0F DTCE0 DTC 8 bits
DTCE7 DTCE6
DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 SBYCR SSBY STS2 STS1 STS0 OPE -- -- IRQ37S Power-down mode 8 bits
H'FF39 H'FF3A
SYSCR SCKCR
--
--
INTM1 DIV
INTM0 --
NMIEG --
LWROD -- SCK2 SCK1
RAME SCK0
MCU Clock pulse generator
8 bits 8 bits
PSTOP --
H'FF3B H'FF3C H'FF3D
MDCR
--
--
--
--
--
MDS2
MDS1
MDS0
MCU
8 bits 8 bits
MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTPCRL MSTP7 MSTP6
MSTP8 Power-down mode
MSTP5
MSTP4 MSTP3 MSTP2
MSTP1 MSTP0
301
Register Address Name H'FF42 H'FF44 H'FF45 H'FF50 H'FF51 H'FF52 H'FF53 H'FF59 H'FF5A H'FF5B H'FF5C H'FF5D H'FF5E H'FF5F H'FF60 H'FF61 H'FF62 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D H'FF6E H'FF6F H'FF70 H'FF71 H'FF72 H'FF73 H'FF74 H'FF76 H'FF77 Bit 7 Bit 6 -- -- Bit 5 -- -- Bit 4 -- -- Bit 3 FLSHE -- Bit 2 -- -- A22E P12 P22 P32 P42 PA2 PB2 PC2 PD2 PE2 PF2 PG2 P12DR P22DR P32DR Bit 1 -- -- A21E P11 P21 P31 P41 PA1 PB1 PC1 PD1 PE1 PF1 PG1 P11DR P21DR P31DR Bit 0 -- -- A20E P10 P20 P30 P40 PA0 PB0 PC0 PD0 PE0 PF0 PG0 P10DR P20DR P30DR Module Name Flash memory Reserved Ports
2 SYSCR2* --
Data Bus Width 8 bits -- 8 bits
Reserved -- PFCR1 PORT1 PORT2 PORT3 PORT4 PORTA PORTB PORTC PORTD PORTE PORTF PORTG P1DR P2DR P3DR PADR PBDR PCDR PDDR PEDR PFDR PGDR PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR
CSS17 CSS36 P17 P27 -- P47 -- PB7 PC7 PD7 PE7 PF7 -- P16 P26 -- P46 -- PB6 PC6 PD6 PE6 PF6 --
PF1CS5S P F0CS 4SA23E P15 P25 P35 P45 -- PB5 PC5 PD5 PE5 PF5 -- P15DR P25DR P35DR -- PB5DR PC5DR PD5DR PE5DR PF5DR -- -- P14 P24 P34 P44 -- PB4 PC4 PD4 PE4 PF4 PG4 P14DR P24DR P34DR -- P13 P23 P33 P43 PA3 PB3 PC3 PD3 PE3 PF3 PG3 P13DR P23DR P33DR
P17DR P16DR P27DR P26DR -- -- -- --
PA3DR PA2DR
PA1DR PA0DR PB1DR PB0DR PC1DR PC0DR PD1DR PD0DR PE1DR PE0DR PF1DR PF0DR
PB7DR PB6DR PC7DR PC6DR PD7DR PD6DR PE7DR PE6DR PF7DR PF6DR -- -- -- --
PB4DR PB3DR PB2DR PC4DR PC3DR PC2DR PD4DR PD3DR PD2DR PE4DR PE3DR PE2DR PF4DR PF3DR PF2DR
PG4DR PG3DR PG2DR PG1DR PG0DR -- PA3PCR PA2PCR PA1PCR PA0PCR
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PC7PCRPC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PD7PCRPD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR -- -- -- -- P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR -- -- PA3ODR PA2ODR PA1ODR PA0ODR
302
Register Address Name H'FF78 SMR0 Bit 7 C/A/ GM* 3 H'FF79 H'FF7A H'FF7B H'FF7C BRR0 SCR0 TDR0 SSR0 TDRE RDRF ORER FER/ ERS*7 H'FF7D H'FF7E H'FF80 RDR0 SCMR0 SMR1 -- C/A/ GM* 3 H'FF81 H'FF82 H'FF83 H'FF84 BRR1 SCR1 TDR1 SSR1 TDRE RDRF ORER FER/ ERS*7 H'FF85 H'FF86 RDR1 SCMR1 -- -- -- -- SDIR SINV -- SMIF PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 -- CHR/ BLK* 4 -- PE -- O/E SDIR STOP/ SINV MP/ -- CKS1 SMIF CKS0 SCI1, smart card interface 1 PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 Bit 6 CHR/ BLK* 4 Bit 5 PE Bit 4 O/E Bit 3 STOP/ Bit 2 MP/ Bit 1 CKS1 Bit 0 CKS0 Module Name SCI0, smart card interface 0
Data Bus Width 8 bits
BCP1* 5 BCP0* 6
8 bits
BCP1* 5 BCP0* 6
303
Register Address Name H'FE90 H'FE91 H'FE92 H'FE93 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 H'FE99 H'FFA4 H'FFA5 H'FFA6 H'FFAC H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBC (Read) H'FFBD (Read) H'FFBF (Read) RSTCSR WOVF RSTE -- -- -- -- -- -- TCNT Bit 7 Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADST Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CKS CKS1 Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- D/A converter Module Name A/D converter
Data Bus Width 8 bits
ADDRAH AD9 ADDRAL AD1 ADDRBH AD9 ADDRBL AD1 ADDRCH AD9 ADDRCL AD1 ADDRDH AD9 ADDRDL AD1 ADCSR ADCR DADR0 DADR1 ADF
TRGS1 TRGS0 --
8 bits
DACR01 DAOE1 DAOE0 DAE PFCR2 TCR0 TCR1 TCSR0 TCSR1 TCORA0 TCORA1 TCORB0 TCORB1 TCNT0 TCNT1 TCSR OVF WT/IT TME -- CMIEB CMIEB CMFB CMFB -- CMIEA CMIEA CMFA CMFA
--
-- ASOD CCLR0 CCLR0 OS3 OS3
-- -- CKS2 CKS2 OS2 OS2
-- -- CKS1 CKS1 OS1 OS1
-- -- CKS0 CKS0 OS0 OS0 Ports 8-bit timer channel 0, 1 8 bits 16 bits
CS167E CS25E OVIE OVIE OVF OVF CCLR1 CCLR1 ADTE --
--
--
CKS2
CKS1
CKS0
WDT
16 bits
304
Register Address Name H'FFC0 H'FFC1 H'FFC8 H'FFC8 H'FFC9 H'FFC9 H'FFCA H'FFCB H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC TGR0C H'FFDD H'FFDE H'FFDF TGR0D TGR0B TGR0A TSTR TSYR Bit 7 -- -- Bit 6 -- -- SWE SWE1 -- SWE2 EB6
9
Data Bus Bit 5 CST5 Bit 4 CST4 Bit 3 CST3 Bit 2 CST2 Bit 1 CST1 Bit 0 CST0 Module Name TPU Width 16 bits
SYNC5 SYNC4 SYNC3 ESU ESU1 -- ESU2 EB5
9
SYNC2 SYNC1 SYNC0 PV PV1 -- PV2 EB2 EB10 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC E E1 -- E2 EB1 EB9 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB P P1 -- P2 EB0 EB8 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU0 16 bits Flash memory 8 bits
FLMCR1 FWE *8 FLMCR1 FWE *9 FLMCR2 FLER *8 FLMCR2 FLER *9 EBR1* 2 EBR2* TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0
2
PSU PSU1 -- PSU2 EB4
8
EV EV1 -- EV2 EB3
8
EB7 EB15*
EB14*
EB13*
EB12*
EB11
CCLR2 -- IOB3 IOD3 TTGE --
CCLR1 -- IOB2 IOD2 -- --
CCLR0 BFB IOB1 IOD1 -- --
CKEG1 CKEG0 BFA IOB0 IOD0 TCIEV TCFV MD3 IOA3 IOC3 TGIED TGFD
305
Register Address Name H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFB TGR2B TGR2A TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 -- -- IOB3 TTGE TCFD CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 CKEG0 TPSC2 -- IOB0 TCIEV TCFV MD3 IOA3 -- -- MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU2 TGR1B TGR1A TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 Bit 7 -- -- IOB3 TTGE TCFD Bit 6 CCLR1 -- IOB2 -- -- Bit 5 CCLR0 -- IOB1 TCIEU TCFU Bit 4 Bit 3 Bit 2 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Module Name TPU1
Data Bus Width 16 bits
CKEG1 CKEG0 TPSC2 -- IOB0 TCIEV TCFV MD3 IOA3 -- -- MD2 IOA2 -- --
16 bits
Notes: 1. Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. 2. Valid only in F-ZTAT version. 3. Functions as C/A for SCI use, and as GM for smart card interface use. 4. Functions as CHR for SCI use, and as BLK for smart card interface use. 5. Functions as STOP for SCI use, and as BCP1 for smart card interface use. 6. Functions as MP for SCI use, and as BCP0 for smart card interface use. 7. Functions as FER for SCI use, and as ERS for smart card interface use. 8. Valid in H8S/2319 F-ZTAT and H8S/2315 F-ZTAT versions. 9. Valid in H8S/2319 F-ZTAT version only.
306
8.2
Module Interrupt controller
List of Registers (By Module)
Register System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Abbreviation R/W SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCR R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W --*
3 2
Initial Value Address* 1 H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3FFF H'FF39 H'FF2C H'FF2D H'FF2E H'FF2F H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE --* 4 --* 4 --* 4 --* 4 --* 4 --* 4 H'FF30 to H'FF34 H'FF37 H'FF3C
DTC
DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable register DTC vector register Module stop control register
--* 3 --* 3 --* 3 --* 3 --* 3 R/W R/W R/W
307
Module Bus controller
Register Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L
Abbreviation R/W ABWCR ASTCR WCRH WCRL BCRH BCRL TCR0 TCSR0 TCORA0 TCORB0 TCNT0 TCR1 TCSR1 TCORA1 TCORB1 TCNT1 MSTPCR R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W
7 7
Initial Value Address* 1 H'FF/H'00* 5 H'FF H'FF H'FF H'D0 H'3C H'00 H'00 H'FF H'FF H'00 H'00 H'10 H'FF H'FF H'00 H'3FFF H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FFB0 H'FFB2 H'FFB4 H'FFB6 H'FFB8 H'FFB1 H'FFB3 H'FFB5 H'FFB7 H'FFB9 H'FF3C
8-bit timer 0
Timer control register 0 Timer control/status register 0 Timer constant register A0 Timer constant register B0 Timer counter 0
8-bit timer 1
Timer control register 1 Timer control/status register 1 Timer constant register A1 Timer constant register B1 Timer counter 1
All 8-bit timer channels WDT
Module stop control register
Timer control/status register
TCSR
R/(W)*9 H'18
H'FFBC: Write* 8 H'FFBC: Read
Timer counter
TCNT
R/W
H'00
H'FFBC: Write* 6 H'FFBD: Read
Reset control/status register
RSTCSR
R/(W)*9 H'1F
H'FFBE: Write* 8 H'FFBF: Read
308
Module SCI0
Register Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0
Abbreviation R/W SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 MSTPCR SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W
2 2 2 2
Initial Value Address* 1 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF3C H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86
SCI1
Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1
All SCI channels SMCI0
Module stop control register Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0
SMCI1
Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1
309
Module All SMCI channels ADC
Register Module stop control register A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register
Abbreviation R/W MSTPCR ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCR DADR0 DADR1 DACR01 MSTPCR SYSCR TCR0 TMDR0 TIOR0H TIOR0L TIER0 TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 R/W R R R R R R R R R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W
2 9
Initial Value Address* 1 H'3FFF H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F H'3FFF H'00 H'00 H'1F H'3FFF H'01 H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'FF3C H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF3C H'FFA4 H'FFA5 H'FFA6 H'FF3C H'FF39 H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD8 H'FFDA H'FFDC H'FFDE H'FFE0 H'FFE1
DAC0, 1
D/A data register 0 D/A data register 1 D/A control register 01
All DAC channels On-chip RAM TPU0
Module stop control register System control register Timer control register 0 Timer mode register 0 Timer I/O control register 0H Timer I/O control register 0L Timer interrupt enable register 0 Timer status register 0 Timer counter 0 Timer general register 0A Timer general register 0B Timer general register 0C Timer general register 0D
TPU1
Timer control register 1 Timer mode register 1
310
Module TPU1
Register Timer I/O control register 1 Timer interrupt enable register 1 Timer status register 1 Timer counter 1 Timer general register 1A Timer general register 1B
Abbreviation R/W TIOR1 TIER1 TSR1 TCNT1 TGR1A TGR1B TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 TGR2A TGR2B TCR3 TMDR3 TIOR3H TIOR3L TIER3 TSR3 TCNT3 TGR3A TGR3B TGR3C TGR3D TCR4 TMDR4 TIOR4 TIER4 TSR4 TCNT4 TGR4A TGR4B R/W R/W
2
Initial Value Address* 1 H'00 H'40 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE8 H'FFEA H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFFA H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE88 H'FE8A H'FE8C H'FE8E H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE98 H'FE9A
R/(W) * H'C0 R/W R/W R/W R/W R/W R/W R/W
2
H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'40
TPU2
Timer control register 2 Timer mode register 2 Timer I/O control register 2 Timer interrupt enable register 2 Timer status register 2 Timer counter 2 Timer general register 2A Timer general register 2B
R/(W) * H'C0 R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W
2 2
H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40
TPU3
Timer control register 3 Timer mode register 3 Timer I/O control register 3H Timer I/O control register 3L Timer interrupt enable register 3 Timer status register 3 Timer counter 3 Timer general register 3A Timer general register 3B Timer general register 3C Timer general register 3D
TPU4
Timer control register 4 Timer mode register 4 Timer I/O control register 4 Timer interrupt enable register 4 Timer status register 4 Timer counter 4 Timer general register 4A Timer general register 4B
R/(W) * H'C0 R/W R/W R/W H'0000 H'FFFF H'FFFF
311
Module TPU5
Register Timer control register 5 Timer mode register 5 Timer I/O control register 5 Timer interrupt enable register 5 Timer status register 5 Timer counter 5 Timer general register 5A Timer general register 5B
Abbreviation R/W TCR5 TMDR5 TIOR5 TIER5 TSR5 TCNT5 TGR5A TGR5B TSTR TSYR MSTPCR FLMCR1*
14
Initial Value Address* 1 H'00 H'C0 H'00 H'40
2
R/W R/W R/W R/W
H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA8 H'FEAA H'FFC0 H'FFC1 H'FF3C
12
R/(W) * H'C0 R/W R/W R/W R/W R/W R/W R/W*
11
H'0000 H'FFFF H'FFFF H'00 H'00 H'3FFF H'00/H'80* H'00 H'00* 13 H'00* 13 H'00 H'00 H'00 H'01 Undefined H'08 H'3F H'FF H'00 H'00 Undefined H'0F H'00 H'00 Undefined
All TPU channels
Timer start register Timer synchro register Module stop control register
Flash memory
Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register System control register 2
H'FFC8* 10 H'FFC9* 10 H'FFCA* 10 H'FFCB* 10 H'FEDB H'FF42 H'FF3A H'FF39 H'FF3B H'FF38 H'FF3C H'FF3D H'FEB0 H'FF60 H'FF50 H'FF45 H'FEB1 H'FF61 H'FF51
FLMCR2* 14 EBR1* 14 EBR2* 14 RAMER SYSCR2* SCKCR SYSCR MDCR SBYCR MSTPCRH MSTPCRL P1DDR P1DR PORT1 PFCR1 P2DDR P2DR PORT2
15
R/W*11 R/W*11 R/W*11 R/W R/W R/W R/W R R/W R/W R/W W R/W R R/W W R/W R
Clock pulse System clock control register generator MCU System control register Mode control register PowerStandby control register down state Module stop control register H Module stop control register L Port 1 Port 1 data direction register Port 1 data register Port 1 register Port function control register 1 Port 2 Port 2 data direction register Port 2 data register Port 2 register
312
Module Port 3
Register Port 3 data direction register Port 3 data register Port 3 register Port 3 open drain control register
Abbreviation R/W P3DDR P3DR PORT3 P3ODR PORT4 PADDR PADR PORTA W R/W R R/W R W R/W R R/W R/W W R/W R R/W W R/W R R/W W R/W R R/W W R/W R R/W W R/W R R/W R/W R/W
Initial Value Address* 1 H'00 H'00 Undefined H'00 Undefined H'0* H'0*
16 16 16
H'FEB2 H'FF62 H'FF52 H'FF76 H'FF53 H'FEB9 H'FF69 H'FF59 H'FF70 H'FF77 H'FEBA H'FF6A H'FF5A H'FF71 H'FEBB H'FF6B H'FF5B H'FF72 H'FEBC H'FF6C H'FF5C H'FF73 H'FEBD H'FF6D H'FF5D H'FF74
17
Port 4 Port A
Port 4 register Port A data direction register Port A data register Port A register
Undefined* H'0* H'0*
16 16
Port A MOS pull-up control register PAPCR Port A open drain control register Port B Port B data direction register Port B data register Port B register PAODR PBDDR PBDR PORTB
H'00 H'00 Undefined H'00 H'00 H'00 Undefined H'00 H'00 H'00 Undefined H'00 H'00 H'00 Undefined H'00 H'80/H'00* H'00 Undefined H'0F H'30 H'01
Port B MOS pull-up control register PBPCR Port C Port C data direction register Port C data register Port C register PCDDR PCDR PORTC
Port C MOS pull-up control register PCPCR Port D Port D data direction register Port D data register Port D register PDDDR PDDR PORTD
Port D MOS pull-up control register PDPCR Port E Port E data direction register Port E data register Port E register PEDDR PEDR PORTE
Port E MOS pull-up control register PEPCR Port F Port F data direction register Port F data register Port F register Port function control register 1 Port function control register 2 System control register PFDDR PFDR PORTF PFCR1 PFCR2 SYSCR
H'FEBE H'FF6E H'FF5E H'FF45 H'FFAC H'FF39
313
Module Port G
Register Port G data direction register Port G data register Port G register Port function control register 1 Port function control register 2
Abbreviation R/W PGDDR PGDR PORTG PFCR1 PFCR2 W R/W R R/W R/W
Initial Value Address* 1 H'10/H'00 * 17 * 18 H'00* 18 Undefined* H'0F H'30
18
H'FEBF H'FF6F H'FF5F H'FF45 H'FFAC
Notes: 1. 2. 3. 4.
5. 6. 7. 8. 9. 10. 11.
12. 13.
14. 15. 16. 17. 18.
Lower 16 bits of the address. Only 0 can be written for flag clearing. Registers in the DTC cannot be read or written to directly. Located as register information in on-chip RAM addresses H'EBC0 to H'EFBF. Cannot be located in external memory space. Do not clear the RAME bit in SYSCR to 0 when using the DTC. Determined by the MCU operating mode. Bits used for pulse output cannot be written to. Only 0 can be written to bits 7 to 5, to clear the flags. For information on writing, see section 10.2.4, Notes on Register Access, in the Hardware Manual. Only 0 can be written to bit 7, to clear the flag. Flash memory registers selection is performed by means of the FLSHE bit in system control register 2 (SYSCR2). In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes are also disabled when the FWE bit in FLMCR1 is cleared to 0. (Except for H8S/2319 F-ZTAT) In H8S/2318 F-ZTAT and H8S/2315 F-ZTAT, when a high level is input to the FWE pin, the initial value is H'80. In H8S/2319 F-ZTAT, the initial value is H'80. In H8S/2318 F-ZTAT and H8S/2315 F-ZTAT, when a low level is input to the FWE pin, or if a high level is input but the SWE bit in FLMCR1 is not set, these registers are initialized to H'00. In the H8S/2319 F-ZTAT, the EB11 to EB0 bits are initialized to 0 when the SWE1 bit is not set to 1, and the EB15 to EB12 bits are initialized to 0 when the SWE2 bit is not set to 1. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte access can be used on these registers, with the access requiring two states. The SYSCR2 register can only be used in the F-ZTAT version. In the mask ROM version this register will return an undefined value if read, and cannot be written to. Value of bits 3 to 0. The initial value depends on the mode. Value of bits 4 to 0.
314
8.3
Functions
H'F800--H'FBFF
5 DM1 -- 4 DM0 -- 3 MD1 -- 2 MD0 -- 1 DTS -- 0 Sz --
MRA--DTC Mode Register A
Bit : 7 SM1 Initial value : Read/Write : -- 6 SM0 --
DTC
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
DTC Data Transfer Size 0 1 Byte-size transfer Word-size transfer
DTC Transfer Mode Select 0 1 DTC Mode 0 0 1 1 0 1 Destination Address Mode 0 1 -- 0 1 Source Address Mode 0 1 -- 0 1 SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Normal mode Repeat mode Block transfer mode -- Destination side is repeat area or block area Source side is repeat area or block area
315
MRB--DTC Mode Register B
Bit : 7 CHNE Initial value : Read/Write : -- 6 DISEL -- 5 CHNS -- 4 -- --
H'F800--H'FBFF
3 -- -- 2 -- -- 1 -- -- 0 -- --
DTC
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Reserved Only 0 should be written to these bits DTC Interrupt Select 0 1 After DTC data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 After DTC data transfer ends, the CPU interrupt is enabled DTC Chain Transfer Select Description No chain transfer. (At end of DTC data transfer, DTC waits for activation) Chain transfer every time Chain transfer only when transfer counter = 0
DTC Chain Transfer Enable CHNE CHNS 0 1 1 -- 0 1
SAR--DTC Source Address Register
Bit : 23 22 21 20 19
H'F800--H'FBFF
--------4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
--
--
--
--
--
--
--
--
--
--
Specifies DTC transfer data source address
316
DAR--DTC Destination Address Register
Bit : 23 22 21 20 19
H'F800--H'FBFF
--------4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
Unde- Unde- Unde- Unde- Undefined fined fined fined fined
--
--
--
--
--
--
--
--
--
--
Specifies DTC transfer data destination address
CRA--DTC Transfer Count Register A
Bit : 15 14 13 12 11 10 9 8
H'F800--H'FBFF
7 6 5 4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
CRAH
CRAL
Specifies the number of DTC data transfers
CRB--DTC Transfer Count Register B
Bit : 15 14 13 12 11 10 9 8
H'F800--H'FBFF
7 6 5 4 3 2 1
DTC
0
Initial value : Read/Write :
Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Specifies the number of DTC block data transfers
317
TCR3--Timer Control Register 3
Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0
H'FE80
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
TPU3
CKEG1 CKEG0 R/W
Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input Internal clock: counts on o/1024 Internal clock: counts on o/256 Internal clock: counts on o/4096
Note: The internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if o/1 or overflow/underflow on another channel is selected as the input clock. Counter Clear 0 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture *2 TCNT cleared by TGRD compare match/input capture *2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1
1
0
0 1
1
0 1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
318
TMDR3--Timer Mode Register 3
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W
H'FE81
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU3
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
* : Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.
Buffer Operation A 0
1
TGRA operates normally
TGRA and TGRC used together for buffer operation
Buffer Operation B 0
1
TGRB operates normally
TGRB and TGRD used together for buffer operation
319
TIOR3H--Timer I/O Control Register 3H
Bit : 7 IOB3 0 Read/Write : R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W
H'FE82
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU3
Initial value :
TGR3A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3A is input capture register Capture input source is TIOCA3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock * : Don't care TGR3B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3B is input capture register Capture input source is TIOCB3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT4 count-up/ count-down*1 * : Don't care Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000, and o/1 is used as the TCNT4 count clock, this setting is invalid and input capture does not occur. TGR3B Output disabled is output compare Initial output is register 0 output TGR3A Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
0 output at compare match 1 output at compare match Toggle output at compare match
320
TIOR3L--Timer I/O Control Register 3L
Bit : 7 IOD3 Initial value : Read/Write : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2
H'FE83
1 IOC1 0 R/W 0 IOC0 0 R/W
TPU3
IOC2 0 R/W
TGR3C I/O Control 0 0 0 0 TGR3C Output disabled is output 1 compare Initial output is 1 0 output 0 register* 1 1 0 0 1 1 0 1 1 0 0 0 TGR3C Capture input is input source is 1 capture TIOCC3 pin 1 * register* * Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges
0 output at compare match 1 output at compare match Toggle output at compare match
1
1 1 *
Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock * : Don't care
Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare does not occur. TGR3D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3D is input capture register *2 Capture input source is TIOCD3 pin Capture input source is channel 4/count clock TGR3D Output disabled is output Initial output is 0 0 output at compare match compare output register 1 output at compare match *2 Toggle output at compare match Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count-up/ count-down*1 * : Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and o/1 is used as the TCNT4 count clock, this setting is invalid and input capture does not occur. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare does not occur. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
321
TIER3--Timer Interrupt Enable Register 3
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3 TGIED 0 R/W
H'FE84
2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W
TPU3
TGR Interrupt Enable A 0 1 Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled
TGR Interrupt Enable C 0 1 Interrupt request (TGIC) by TGFC bit disabled Interrupt request (TGIC) by TGFC bit enabled
TGR Interrupt Enable D 0 1 Interrupt request (TGID) by TGFD bit disabled Interrupt request (TGID) by TGFD bit enabled
Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
322
TSR3--Timer Status Register 3
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)*
H'FE85
2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU3
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT=TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Input Capture/Output Compare Flag C 0 [Clearing conditions] * When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register
1
Input Capture/Output Compare Flag D 0 [Clearing conditions] * When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register
1
Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
323
TCNT3--Timer Counter 3
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0
H'FE86
8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU3
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
TGR3A--Timer General Register 3A TGR3B--Timer General Register 3B TGR3C--Timer General Register 3C TGR3D--Timer General Register 3D
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1
H'FE88 H'FE8A H'FE8C H'FE8E
8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU3 TPU3 TPU3 TPU3
0 1
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
324
TCR4--Timer Control Register 4
Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W
H'FE90
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
TPU4
CKEG1 CKEG0
Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on o/1024 Counts on TCNT5 overflow/underflow
Clock Edge 0 0 1 1 --
Note: This setting is ignored when channel 4 is in phase counting mode.
Count at rising edge Count at falling edge Count at both edges
Note: This setting is ignored when channel 4 is in phase counting mode. The internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if o/1 or overflow/underflow on another channel is selected as the input clock.
Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
325
TMDR4--Timer Mode Register 4
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 --
H'FE91
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU4
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
* : Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0.
326
TIOR4--Timer I/O Control Register 4
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2
H'FE92
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU4
IOA2 0 R/W
TGR4A I/O Control
0 0 0
1
0 TGR4A Output disabled is output 1 compare Initial output is 0 output 0 register 1
0 output at compare match 1 output at compare match Toggle output at compare match
1
0
0 1
Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR4A is input capture register Capture input source is TIOCA4 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3A TGR3A compare match/input compare match/ capture input capture * : Don't care
1
0 1
1
0
0
0 1
1 1 *
* *
TGR4B I/O Control 0 0 0 0 TGR4B Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * *
TGR4B is input capture register Capture input source is TIOCB4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3C TGR3C compare match/input compare match/ capture input capture
0 output at compare match 1 output at compare match Toggle output at compare match
1
* : Don't care
327
TIER4--Timer Interrupt Enable Register 4
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 --
H'FE94
2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1
TPU4
Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt request (TCIU) by TCFU disabled Interrupt request (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
328
TSR4--Timer Status Register 4
Bit : 7 TCFD Initial value : Read/Write : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 --
H'FE95
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU4
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000)
Note: * Can only be written with 0 for flag clearing.
329
TCNT4--Timer Counter 4
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0
H'FE96
8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU4
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR4A--Timer General Register 4A TGR4B--Timer General Register 4B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1
H'FE98 H'FE9A
8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU4 TPU4
0 1
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
330
TCR5--Timer Control Register 5
Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W
H'FEA0
2 TPSC2 0 R/W
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64
TPU5
1 TPSC1 0 R/W 0 TPSC0 0 R/W
CKEG1 CKEG0
External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on o/256 External clock: counts on TCLKD pin input
Note: This setting is ignored when channel 5 is in phase counting mode.
Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges
Note: This setting is ignored when channel 5 is in phase counting mode. The internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if o/1 or overflow/underflow on another channel is selected as the input clock.
Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
331
TMDR5--Timer Mode Register 5
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 --
H'FEA1
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU5
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
* : Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0.
332
TIOR5--Timer I/O Control Register 5
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2
H'FEA2
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU5
IOA2 0 R/W
TGR5A I/O Control 0 0 0 0 TGR5A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR5A is input 1 capture * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at rising edge source is TIOCA5 Input capture at falling edge pin Input capture at both edges
* : Don't care
0 output at compare match 1 output at compare match Toggle output at compare match
1
1
TGR5B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR5B is input capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at rising edge source is TIOCB5 Input capture at falling edge pin Input capture at both edges
* : Don't care
TGR5B Output disabled is output compare Initial output is 0 register output
0 output at compare match 1 output at compare match Toggle output at compare match
333
TIER5--Timer Interrupt Enable Register 5
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 --
H'FEA4
2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1
TPU5
Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt request (TCIU) by TCFU disabled Interrupt request (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
334
TSR5--Timer Status Register 5
Bit : 7 TCFD Initial value : Read/Write : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 --
H'FEA5
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU5
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
335
TCNT5--Timer Counter 5
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FEA6
7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU5
0 0
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR5A--Timer General Register 5A TGR5B--Timer General Register 5B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1
H'FEA8 H'FEAA
8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU5 TPU5
0 1
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
P1DDR--Port 1 Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEB0
3 0 W 2 0 W 1 0 W 0 0 W
Port 1
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : Read/Write :
Specify input or output for individual port 1 pins
336
P2DDR--Port 2 Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEB1
3 0 W 2 0 W 1 0 W 0 0
Port 2
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : Read/Write : W
Specify input or output for individual port 2 pins
P3DDR--Port 3 Data Direction Register
Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 0 W 4 0 W
H'FEB2
3 0 W 2 0 W 1 0 W 0 0
Port 3
P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR W
Undefined Undefined
Specify input or output for individual port 3 pins
PADDR--Port A Data Direction Register
Bit Initial value Read/Write : : : 7 -- -- 6 -- -- 5 -- -- 4 -- --
H'FEB9
3 0 W 2 0 W 1 0 W
Port A
0 0 W
PA3DDR PA2DDR PA1DDR PA0DDR
Undefined Undefined Undefined Undefined
Specify input or output for individual port A pins
337
PBDDR--Port B Data Direction Register
Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBA
3 0 W 2 0 W 1 0 W 0 0
Port B
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR W
Specify input or output for individual port B pins
PCDDR--Port C Data Direction Register
Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBB
3 0 W 2 0 W 1 0 W
Port C
0 0 W
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Specify input or output for individual port C pins
PDDDR--Port D Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBC
3 0 W 2 0 W 1 0 W
Port D
0 0 W
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : Read/Write :
Specify input or output for individual port D pins
PEDDR--Port E Data Direction Register
Bit : 7 0 W 6 0 W 5 0 W 4 0 W
H'FEBD
3 0 W 2 0 W 1 0 W
Port E
0 0 W
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : Read/Write :
Specify input or output for individual port E pins 338
PFDDR--Port F Data Direction Register
Bit Modes 4 to 6* Initial value Read/Write Mode 7* Initial value Read/Write : : 0 W 0 W 0 W 0 W : : 1 W 0 W 0 W 0 W : 7 6 5 4
H'FEBE
3 2 1 0
Port F
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Specify input or output for individual port F pins Note: * Modes 6 and 7 cannot be used in the ROMless version.
PGDDR--Port G Data Direction Register
Bit : 7 -- Modes 4 and 5 Initial value Read/Write Initial value Read/Write : Undefined Undefined Undefined : -- -- -- 1 W 0 W 6 -- 5 -- 4
H'FEBF
3 2 1
Port G
0
PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W
Modes 6 and 7* : Undefined Undefined Undefined : -- -- --
Specify input or output for individual port G pins Note: * Modes 6 and 7 cannot be used in the ROMless version.
339
IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK
Bit
-- -- -- -- -- -- -- -- -- -- --
Interrupt Priority Register A Interrupt Priority Register B Interrupt Priority Register C Interrupt Priority Register D Interrupt Priority Register E Interrupt Priority Register F Interrupt Priority Register G Interrupt Priority Register H Interrupt Priority Register I Interrupt Priority Register J Interrupt Priority Register K
: 7 -- 0 -- 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W
H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE
3 -- 0 -- 2 IPR2 1 R/W
Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller
1 IPR1 1 R/W 0 IPR0 1 R/W
Initial value : Read/Write :
Set priority (levels 7 to 0) for interrupt sources Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 IPRA IPRB IRQ0 IRQ2 IRQ3 IPRC IRQ6 IRQ7 IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK WDT --* TPU channel 0 TPU channel 2 TPU channel 4 8-bit timer channel 0 --* SCI channel 1 --* A/D converter TPU channel 1 TPU channel 3 TPU channel 5 8-bit timer channel 1 SCI channel 0 --* IRQ1 IRQ4 IRQ5 DTC 2 to 0
Note: * Reserved bits.
340
ABWCR--Bus Width Control Register
Bit : 7 ABW7 Modes 5 to 7* Initial value : R/W Mode 4 Initial value : Read/Write : 0 R/W 0 R/W 0 R/W 0 R/W : 1 R/W 1 R/W 1 R/W 1 R/W 6 ABW6 5 ABW5 4
H'FED0
3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1
Bus Controller
0 ABW0 1 R/W 0 R/W
ABW4
ABW1 1 R/W 0 R/W
Area 7 to 0 Bus Width Control 0 1 Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0)
Note: * Modes 6 and 7 cannot be used in the ROMless version.
ASTCR--Access State Control Register
Bit : 7 AST7 Initial value : Read/Write : 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W
H'FED1
3 AST3 1 R/W 2 AST2 1 R/W 1
Bus Controller
0 AST0 1 R/W
AST1 1 R/W
Area 7 to 0 Access State Control 0 Area n is designated for 2-state access Wait state insertion in area n external space is disabled 1 Area n is designated for 3-state access Wait state insertion in area n external space is enabled (n = 7 to 0)
341
WCRH--Wait Control Register H
Bit : 7 W71 Initial value : Read/Write : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3
H'FED2
2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W
Bus Controller
W51 1 R/W
Area 4 Wait Control 0 0 1 1 0 1 Area 5 Wait Control 0 0 1 1 0 1 Area 6 Wait Control 0 0 1 1 0 1 Area 7 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted
342
WCRL--Wait Control Register L
Bit : 7 W31 Initial value : Read/Write : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3
H'FED3
2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W
Bus Controller
W11 1 R/W
Area 0 Wait Control 0 0 1 1 0 1 Area 1 Wait Control 0 0 1 1 0 1 Area 2 Wait Control 0 0 1 1 0 1 Area 3 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted
343
BCRH--Bus Control Register H
Bit : 7 ICIS1 Initial value : Read/Write : 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W
H'FED4
3 0 R/W 2 -- 0 R/W 1 -- 0 R/W
Bus Controller
0 -- 0 R/W
BRSTRM BRSTS1 BRSTS0
Reserved Only 0 should be written to these bits
Burst Cycle Select 0 0 1 Max. 4 words in burst access Max. 8 words in burst access
Burst Cycle Select 1 0 1 Burst cycle comprises 1 state Burst cycle comprises 2 states
Area 0 Burst ROM Enable 0 1 Basic bus interface Burst ROM interface
Idle Cycle Insert 0 0 1 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles
Idle Cycle Insert 1 0 1 Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas
344
BCRL--Bus Control Register L
Bit : 7 BRLE Initial value : Read/Write : 0 R/W 6 BREQOE 0 R/W 5 EAE 1 R/W 4 -- 1 R/W
H'FED5
3 -- 1 R/W 2 -- 1 R/W 1 -- 0 R/W 0
Bus Controller
WAITE 0 R/W
WAIT Pin Enable 0 Wait input by WAIT pin disabled Wait input by WAIT pin enabled
1
Reserved (Only 0 should be written to this bit.) Reserved (Only 1 should be written to these bit.) External Address Enable 0 Addresses H'010000 to H'03FFFF*2: * H8S/2319 and H8S/2315: On-chip ROM * H8S/2318: On-chip ROM * H8S/2317: On-chip ROM at addresses H'010000 to H'01FFFF and reserved area*1 at addresses H'020000 to H'03FFFF * H8S/2311, H8S/2313, and H8S/2316: Reserved area*1 Addresses H'010000 to H'03FFFF*2: * Expanded mode: External addresses * Single-chip mode: Reserved area*1
1
Notes: 1. Do not access a reserved area. 2. H'010000 to H'05FFFF in the H8S/2315, and H'010000 to H'07FFFF in the H8S/2319. BREQO Pin Enable 0 1 BREQO output disabled BREQO output enabled
Bus Release Enable 0 1 External bus release disabled External bus release enabled
345
RAMER--RAM Emulation Register
H'FEDB
Flash Memory (Valid only in F-ZTAT version)
2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W
Bit
:
7 -- 0 --
6 -- 0 --
5 -- 0 --
4 -- 0 --
3 RAMS 0 R/W
Initial value : Read/Write :
RAM Select, Flash Memory Area Select RAMS RAM2 RAM1 RAM0 0 1 * 0 * 0 1 1 0 1 *: Don't care * 0 1 0 1 0 1 0 1 RAM Area H'FFDC00 to H'FFEBFF H'000000 to H'000FFF H'001000 to H'001FFF H'002000 to H'002FFF H'003000 to H'003FFF H'004000 to H'004FFF H'005000 to H'005FFF H'006000 to H'006FFF H'007000 to H'007FFF Block Name RAM area, 4 kbytes EB0 (4 kbytes) EB1 (4 kbytes) EB2 (4 kbytes) EB3 (4 kbytes) EB4 (4 kbytes) EB5 (4 kbytes) EB6 (4 kbytes) EB7 (4 kbytes)
346
ISCRH -- IRQ Sense Control Register H ISCRL -- IRQ Sense Control Register L
ISCRH Bit : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W
H'FF2C H'FF2D
Interrupt Controller Interrupt Controller
11 0 R/W
10 0 R/W
9 0 R/W
8 0 R/W
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : Read/Write :
IRQ7 to IRQ4 Sense Control A, B ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : Read/Write :
IRQ3 to IRQ0 Sense Control A, B IRQnSCB IRQnSCA 0 0 1 1 0 1 Interrupt Request Generation IRQn input low level Falling edge of IRQn input Rising edge of IRQn input Both falling and rising edges of IRQn input (n = 7 to 0)
347
IER--IRQ Enable Register
Bit : 7 IRQ7E Initial value : Read/Write : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4
H'FF2E
3 IRQ3E 0 R/W 2 IRQ2E 0 R/W
Interrupt Controller
1 IRQ1E 0 R/W 0 IRQ0E 0 R/W
IRQ4E 0 R/W
IRQn Enable 0 1 IRQn interrupt disabled IRQn interrupt enabled (n = 7 to 0)
348
ISR--IRQ Status Register
Bit : 7 IRQ7F Initial value : Read/Write : 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4
H'FF2F
3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)*
Interrupt Controller
1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)*
IRQ4F 0 R/(W)*
Indicate the status of IRQ7 to IRQ0 interrupt requests Bit n IRQnF 0
Description [Clearing conditions] * * * * When 0 is written to IRQnF after reading IRQnF = 1 When interrupt exception handling is executed while low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high When IRQn interrupt exception handling is executed while falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When the DTC is activated by an IRQn interrupt and the DISEL bit in the DTC's MRB register is 0 When IRQn input goes low while low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input while falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input while rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input while both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0) (Initial value)
1
[Setting conditions] * * * *
Note: * Can only be written with 0 for flag clearing.
349
DTCERA to DTCERF--DTC Enable Registers
Bit : 7 DTCE7 Initial value : Read/Write : 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W
H'FF30 to H'FF34
3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0
DTC
DTCE0 0 R/W
DTC Activation Enable
0 DTC activation by this interrupt is disabled [Clearing conditions] * When the DISEL bit is 1 and data transfer has ended * When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended
1
Correspondence between Interrupt Sources and DTCER
Bits Register DTCERA DTCERB DTCERC DTCERD DTCERE 7 IRQ0 -- TGI2A -- -- 6 IRQ1 ADI TGI2B -- -- 5 IRQ2 TGI0A TGI3A TGI5A -- 4 IRQ3 TGI0B TGI3B TGI5B -- 3 IRQ4 TGI0C TGI3C CMIA0 RXI0 2 IRQ5 TGI0D TGI3D CMIB0 TXI0 1 IRQ6 TGI1A TGI4A CMIA1 RXI1 0 IRQ7 TGI1B TGI4B CMIB1 TXI1
Note: For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register.
350
DTVECR--DTC Vector Register
Bit : 7 0 R/W 6 0 R/(W)* 5 0 R/(W)* 4 0 R/(W)*
H'FF37
3 0 R/(W)* 2 0 R/(W)* 1 0 R/(W)* 0 0
DTC
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : Read/Write : R/(W)*
Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing conditions] * When the DISEL bit is 0 and the specified number of transfers have not ended * When 0 is written to the SWDTE bit after a software activated data transfer end interrupt (SWDTEND) has been requested of the CPU DTC software activation is enabled [Holding conditions] * When the DISEL bit is 1 and data transfer has ended * When the specified number of transfers have ended * During data transfer due to software activation
1
Note: * Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
351
SBYCR--Standby Control Register
Bit : 7 SSBY Initial value : Read/Write : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W
H'FF38
3 OPE 1 R/W 2 -- 0 -- 1 -- 0 --
Power-Down State
0 IRQ37S 0 R/W
IRQ37 Software Standby Clear Select 0 1 IRQ3 to IRQ7 cannot be used as software standby mode clearing sources IRQ3 to IRQ7 can be used as software standby mode clearing sources
Output Port Enable 0 1 In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state
Standby Timer Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states*
Note: * Cannot be used in the F-ZTAT version. Software Standby 0 1 Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction
352
SYSCR--System Control Register
Bit : 7 -- Initial value : Read/Write : 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W
H'FF39
3 0 R/W 2 0 R/W 1 -- 0 R/W 0 RAME 1 R/W
MCU
NMIEG LWROD
RAM Enable 0 1 On-chip RAM disabled On-chip RAM enabled
Reserved Only 0 should be written to this bit LWR Output Disable 0 1 PF3 is designated as LWR output pin PF3 is designated as I/O port, and does not function as LWR output pin
NMI Input Edge Select 0 1 Falling edge Rising edge
Interrupt Control Mode Selection 0 0 1 1 0 1 Interrupt control mode 0 Setting prohibited Interrupt control mode 2 Setting prohibited
Reserved Only 0 should be written to this bit
353
SCKCR--System Clock Control Register
Bit : 7 PSTOP Initial value : Read/Write : 0 R/W 6 -- 0 R/W 5 DIV 0 R/W Division Ratio Select Reserved Only 0 should be written to this bit System Clock Select DIV = 0 0 0 0 1 1 0 1 1 0 0 1 1 -- 4 -- 0 -- 3 -- 0 --
H'FF3A
2 SCK2 0 R/W 1 SCK1 0 R/W
Clock Pulse Generator
0 SCK0 0 R/W
DIV = 1
Bus master is in high-speed mode Bus master is in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- Clock supplied to entire chip is o/2 Clock supplied to entire chip is o/4 Clock supplied to entire chip is o/8 -- -- --
o Clock Output Control PSTOP 0 1 Normal Operation o output Fixed high Sleep Mode o output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance
354
MDCR--Mode Control Register
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 --
H'FF3B
3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0
MCU
MDS0 --* R
Current mode pin operating mode Note: * Determined by pins MD2 to MD0
MSTPCRH -- Module Stop Control Register H MSTPCRL -- Module Stop Control Register L
MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1
H'FF3C H'FF3D
Power-Down State Power-Down State
MSTPCRL
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Specifies module stop mode 0 1 Module stop mode cleared Module stop mode set
MSTP Bits and On-Chip Supporting Modules Register MSTPCRH Bits MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Module -- DTC TPU 8-bit timer -- D/A A/D -- -- SCI1 SCI0 -- -- -- -- --
MSTPCRL
355
SYSCR2--System Control Register 2
H'FF42
Flash Memory (Valid only in F-ZTAT version))
2 -- 0 -- 1 -- 0 -- 0 -- 0 --
Bit
:
7 -- 0 --
6 -- 0 --
5 -- 0 --
4 -- 0 --
3 FLSHE 0 R/W
Initial value : Read/Write :
Flash Memory Control Register Enable 0 1 Flash memory control register is not selected for area H'FFFFC8 to H'FFFFCB Flash memory control register is selected for area H'FFFFC8 to H'FFFFCB
Reserved Register
Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 -- 0 R/W 4 -- 0 --
H'FF44
3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 --
Reserved Only 0 should be written to these bits
356
PFCR1--Port Function Control Register 1
Bit : 7 CSS17 Initial value : Read/Write : 0 R/W 6 CSS36 0 R/W 5 0 R/W 4 0 R/W
H'FF45
3 A23E 1 R/W 2 A22E 1 R/W 1 A21E 1 R/W 0 A20E 1 R/W
PF1CC5S PF0CS45
Address 20 Output Enable*1 0 1 P10DR is output when P10DDR = 1 A20 is output when P10DDR = 1
Address 21 Output Enable*1 0 1 P11DR is output when P11DDR = 1 A21 is output when P11DDR = 1
Address 22 Output Enable*1 0 1 P12DR is output when P12DDR = 1 A22 is output when P12DDR = 1
Address 23 Output Enable*1 0 1 P13DR is output when P13DDR = 1 A23 is output when P13DDR = 1
Port F0 chip select 4 select*1 0 1 PF0 is PF0/BREQ/IRQ0 pin PF0 is PF0/BREQ/IRQ0/CS4 pin. CS4 output is enabled when BRLE = 0, CS25E = 1, and PF0DDR = 1 Port F1 chip select 5 select*1 0 1 PF1 is PF1/BACK/IRQ1 pin PF1 is PF1/BACK/IRQ1/CS5 pin. CS5 output is enabled when BRLE = 0, CS25E = 1, and PF1DDR = 1 CS36 select*1, *3 0 1 0 1 PG1 is PG1/IRQ7/CS3 pin. CS3 output is enabled when when CS25E = 1 and PG1DDR = 1 PG1 is PG1/IRQ7/CS6 pin. CS6 output is enabled when CS167E = 1 and PG1DDR = 1
CS17 select*1, *2 PG3 is PG3/CS1 pin. CS1 output is enabled when CS167E = 1 and PG3DDR = 1 PG3 is PG3/CS7 pin. CS7 output is enabled when CS167E = 1 and PG3DDR = 1
Notes: 1. Valid in modes 4 to 6. 2. Clear PG3DDR to 0 before changing the CSS17 bit setting. 3. Clear PG1DDR to 0 before changing the CSS36 bit setting.
357
PORT1--Port 1 Register
Bit : 7 P17 Initial value : Read/Write : --* R 6 P16 --* R 5 P15 --* R 4 P14 --* R
H'FF50
3 P13 --* R 2 P12 --* R 1 P11 --* R 0
Port 1
P10 --* R
State of port 1 pins
Note: * Determined by the state of pins P17 to P10.
PORT2--Port 2 Register
Bit : 7 P27 Initial value : Read/Write : --* R 6 P26 --* R 5 P25 --* R 4 P24 --* R
H'FF51
3 P23 --* R 2 P22 --* R 1 P21 --* R 0
Port 2
P20 --* R
State of port 2 pins Note: * Determined by the state of pins P27 to P20.
PORT3--Port 3 Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 P35 --* R 4 P34 --* R
H'FF52
3 P33 --* R 2 P32 --* R 1 P31 --* R 0
Port 3
P30 --* R
Initial value : Undefined Undefined
State of port 3 pins Note: * Determined by the state of pins P35 to P30.
358
PORT4--Port 4 Register
Bit : 7 P47 Initial value : Read/Write : --* R 6 P46 --* R 5 P45 --* R 4 P44 --* R
H'FF53
3 P43 --* R 2 P42 --* R 1 P41 --* R 0
Port 4
P40 --* R
State of port 4 pins Note: * Determined by the state of pins P47 to P40.
PORTA--Port A Register
Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 -- -- 4 -- --
H'FF59
3 PA3 --* R 2 PA2 --* R 1 PA1 --* R
Port A
0 PA0 --* R
Undefined Undefined Undefined Undefined
State of port A pins Note: * Determined by the state of pins PA3 to PA0.
PORTB--Port B Register
Bit : 7 PB7 Initial value : Read/Write : --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R
H'FF5A
3 PB3 --* R 2 PB2 --* R 1 PB1 --* R
Port B
0 PB0 --* R
State of port B pins Note: * Determined by the state of pins PB7 to PB0.
359
PORTC--Port C Register
Bit : 7 PC7 Initial value : Read/Write : --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R
H'FF5B
3 PC3 --* R 2 PC2 --* R 1 PC1 --* R
Port C
0 PC0 --* R
State of port C pins Note: * Determined by the state of pins PC7 to PC0.
PORTD--Port D Register
Bit : 7 PD7 Initial value : Read/Write : --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R
H'FF5C
3 PD3 --* R 2 PD2 --* R 1 PD1 --* R
Port D
0 PD0 --* R
State of port D pins Note: * Determined by the state of pins PD7 to PD0.
PORTE--Port E Register
Bit : 7 PE7 Initial value : Read/Write : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R
H'FF5D
3 PE3 --* R 2 PE2 --* R 1 PE1 --* R
Port E
0 PE0 --* R
State of port E pins Note: * Determined by the state of pins PE7 to PE0.
360
PORTF--Port F Register
Bit : 7 PF7 Initial value : Read/Write : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R
H'FF5E
3 PF3 --* R 2 PF2 --* R 1 PF1 --* R 0
Port F
PF0 --* R
State of port F pins Note: * Determined by the state of pins PF7 to PF0.
PORTG--Port G Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 PG4 --* R
H'FF5F
3 PG3 --* R 2 PG2 --* R 1 PG1 --* R
Port G
0 PG0 --* R
Initial value : Undefined Undefined Undefined
State of port G pins Note: * Determined by the state of pins PG4 to PG0.
P1DR--Port 1 Data Register
Bit : 7 P17DR Initial value : Read/Write : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4
H'FF60
3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0
Port 1
P14DR 0 R/W
P10DR 0 R/W
Stores output data for port 1 pins (P17 to P10)
P2DR--Port 2 Data Register
Bit : 7 P27DR Initial value : Read/Write : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4
H'FF61
3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0
Port 2
P24DR 0 R/W
P20DR 0 R/W
Stores output data for port 2 pins (P27 to P20) 361
P3DR--Port 3 Data Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 P35DR 0 R/W 4
H'FF62
3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W
Port 3
0 P30DR 0 R/W
P34DR 0 R/W
Initial value : Undefined Undefined
Stores output data for port 3 pins (P35 to P30)
PADR--Port A Data Register
Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 -- -- 4 -- --
H'FF69
3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W
Port A
0 PA0DR 0 R/W
Undefined Undefined Undefined Undefined
Stores output data for port A pins (PA3 to PA0)
PBDR--Port B Data Register
Bit : 7 PB7DR Initial value : Read/Write : 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF6A
3 0 R/W 2 0 R/W 1 0 R/W 0 0
Port B
PB6DR PB5DR PB4DR PB3DR PB2DR
PB1DR PB0DR R/W
Stores output data for port B pins (PB7 to PB0)
PCDR--Port C Data Register
Bit : 7 PC7DR Initial value : Read/Write : 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF6B
3 0 R/W 2 0 R/W 1 0 R/W
Port C
0 0 R/W
PC6DR PC5DR PC4DR PC3DR PC2DR
PC1DR PC0DR
Stores output data for port C pins (PC7 to PC0) 362
PDDR--Port D Data Register
Bit : 7 PD7DR Initial value : Read/Write : 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF6C
3 0 R/W 2 PD2DR 0 R/W 1 0 R/W
Port D
0 0 R/W
PD6DR PD5DR
PD4DR PD3DR
PD1DR PD0DR
Stores output data for port D pins (PD7 to PD0)
PEDR--Port E Data Register
Bit : 7 PE7DR Initial value : Read/Write : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4
H'FF6D
3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W
Port E
0 PE0DR 0 R/W
PE4DR 0 R/W
Stores output data for port E pins (PE7 to PE0)
PFDR--Port F Data Register
Bit : 7 PF7DR Initial value : Read/Write : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4
H'FF6E
3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W
Port F
0 PF0DR 0 R/W
PF4DR 0 R/W
Stores output data for port F pins (PF7 to PF0)
363
PGDR--Port G Data Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 0 R/W
H'FF6F
3 0 R/W 2 0 R/W 1 0 R/W 0 0
Port G
PG4DR PG3DR PG2DR PG1DR PG0DR R/W
Initial value : Undefined Undefined Undefined
Stores output data for port G pins (PG4 to PG0)
PAPCR--Port A MOS Pull-Up Control Register
Bit : 7 6 5 4
H'FF70
3 0 R/W 2 0 R/W 1 0 R/W 0 0
Port A
--
Initial value : Read/Write :
-- --
-- --
-- --
PA3PCR PA2PCR PA1PCR PA0PCR R/W
Undefined Undefined Undefined Undefined --
Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis
PBPCR--Port B MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF71
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Port B
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : Read/Write :
Controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis
364
PCPCR--Port C MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF72
3 0 R/W 2 0 R/W 1 0 R/W 0 0
Port C
PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : Read/Write : R/W
Controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis
PDPCR--Port D MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF73
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Port D
PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : Read/Write :
Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis
PEPCR--Port E MOS Pull-Up Control Register
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FF74
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Port E
PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : Read/Write :
Controls the MOS input pull-up function incorporated into port E on a bit-by-bit basis
365
P3ODR--Port 3 Open Drain Control Register
Bit : 7 -- Read/Write : -- 6 -- -- 5 0 R/W 4 0 R/W
H'FF76
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Port 3
P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
Initial value : Undefined Undefined
Controls the PMOS on/off status for each port 3 pin (P35 to P30)
PAODR--Port A Open Drain Control Register
Bit : 7 6 5 4
H'FF77
3 0 R/W 2 0 R/W 1 0 R/W
Port A
0 0 R/W
--
Initial value : Read/Write :
-- --
-- --
-- --
PA3ODR PA2ODR PA1ODR PA0ODR
Undefined Undefined Undefined Undefined --
Controls the PMOS on/off status for each port A pin (PA3 to PA0)
366
SMR0--Serial Mode Register 0
Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3
H'FF78
2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCI0
STOP 0 R/W
Clock Select 0 0 1 1 0 1 o clock o/4 clock o/16 clock o/64 clock
Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Even parity*1 Odd parity*2 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined. 2. When odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined. Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled*
Notes: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Character Length 0 1 8-bit data 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. With 7-bit data, it is not possible to select LSB-first or MSB-first transfer. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode
367
SMR0--Serial Mode Register 0
Bit : 7 GM Initial value : Read/Write : 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3
H'FF78
2 BCP0 0 R/W 1 CKS1 0 R/W
Smart Card Interface 0
0 CKS0 0 R/W
BCP1 0 R/W
Clock Select 0 0 1 1 0 1 Base Clock Pulse BCP1 BCP0 0 0 1 1 0 1 Parity Mode 0 1 Even parity*1 Odd parity*2 Base Clock Pulse 32 clocks 64 clocks 372 clocks 256 clocks o clock o/4 clock o/16 clock o/64 clock
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined. 2. When odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined. Parity Enable (Set to 1 when using the smart card interface) 0 1 Setting prohibited Parity bit addition and checking enabled
Block Transfer Mode Select 0 1 GSM Mode 0 Normal smart card interface mode operation * TEND flag generated 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit * Clock output on/off control only GSM mode smart card interface mode operation * TEND flag generated 11.0 etu after beginning of start bit * Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control Normal smart card interface mode Block transfer mode
1
Note: etu (Elementary Time Unit): Interval for transfer of one bit
368
BRR0--Bit Rate Register 0
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF79
3 1 R/W
SCI0, Smart Card Interface 0
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Sets the serial transfer bit rate Note: For details, see section 11.2.8, Bit Rate Register (BRR), in the Hardware Manual.
369
SCR0--Serial Control Register 0
Bit :
7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF7A
1 CKE1 0 R/W Clock Enable 0 CKE0 0 R/W
SCI0
Initial value : Read/Write :
0
0
Asynchronous mode Synchronous mode
Internal clock/SCK pin functions as I/O port
Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input
1
Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode
1
0
1
Transmit End Interrupt Enable
0 1 Transmit-end interrupt (TEI) request disabled*3
Transmit-end interrupt (TEI) request enabled*3
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received Multiprocessor interrupts enabled*4 Receive-data-full interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled*5 Reception enabled*6
Transmit Enable 0 1 Transmission disabled*7 Transmission enabled*8
Receive Interrupt Enable 0 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled*9 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled*10 Transmit-data-empty interrupt (TXI) request enabled
370
Notes: 1. Outputs a clock of the same frequency as the bit rate.
2. Inputs a clock with a frequency 16 times the bit rate.
3. TEI clearing can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. 4. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. 5. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 6. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR setting must be performed to decide the receive format before setting the RE bit to 1. 7. The TDRE flag in SSR is fixed at 1. 8. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transmit format before setting the TE bit to 1. 9. RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. 10. TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0.
371
SCR0--Serial Control Register 0
Bit :
7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF7A
1 CKE1 0 R/W 0 CKE0 0 R/W
Smart Card Interface 0
Initial value : Read/Write :
Clock Enable (When bit 7 of SMR is set to 1 in smart card interface mode) SMCR SMR SCR setting SCK pin function SMIF C/A,GM CKE1 CKE0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 See SCI specification 0 1 0 1 0 1
Operates as port I/O pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin
Transmit End Interrupt Enable 0 1 Transmit-end interrupt (TEI) request disabled*1 Transmit-end interrupt (TEI) request enabled*1
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received Multiprocessor interrupts enabled*2 Receive-data-full interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled*3 Reception enabled*4
Transmit Enable 0 1 Transmission disabled*5 Transmission enabled*6
Receive Interrupt Enable 0 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled*7 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled*8 Transmit-data-empty interrupt (TXI) request enabled
372
Notes: 1. TEI clearing can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. 2. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. 3. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 4. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR setting must be performed to decide the receive format before setting the RE bit to 1. 5. The TDRE flag in SSR is fixed at 1. 6. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transmit format before setting the TE bit to 1. 7. RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. 8. TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0.
TDR0--Transmit Data Register 0
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1
H'FF7B
3 1 R/W
SCI0, Smart Card Interface 0
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
R/W
Stores data for serial transmission
373
SSR0--Serial Status Register 0
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)*1
6 RDRF 0 5 ORER 0 4 FER 0 3 PER 0 2 TEND 1 R
H'FF7C
1 MPB 0 R 0 MPBT 0 R/W
SCI0
R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1
Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received*2 [Setting condition] When data with a 1 multiprocessor bit is received
1
Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1*3 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR*4
Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1*5 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0*6
Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1*7 [Setting condition] When the next serial reception is completed while RDRF = 1*8
Receive Data Register Full*9 0
[Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0
[Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR
1
374
Notes: 1. Can only be written with 0 for flag clearing. 2. Retains its previous state when the RE bit in SCR is cleared to 0 with a multiprocessor format. 3. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 4. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial reception cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission is also disabled. 5. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 6. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial reception cannot be continued while the FER flag is set to 1. In synchronous mode, serial transmission is also disabled. 7. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 8. The receive data prior to the overrun error is retained in RDR, and data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission is also disabled. 9. RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost.
375
SSR0--Serial Status Register 0
Bit :
7 TDRE 1 R/(W)*1 6 RDRF 0 5 ORER 0 4 ERS 0 3 PER 0 2 TEND 1 R
H'FF7C
1 MPB 0 R 0 MPBT 0 R/W
Smart Card Interface 0
Initial value : Read/Write :
R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1
Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit 0 1 Transmit End 0 Transmission in progress [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR Transmission has ended [Setting conditions] * On reset, or in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is 0 * When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu*3 after transmission of a 1-byte serial character when GM = 0 and BLK = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 [Clearing condition] When data with a 0 multiprocessor bit is received*2 [Setting condition] When data with a 1 multiprocessor bit is received
1
Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1*4 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR*5
Error Signal Status*6 0 Data has been received normally, and there is no error signal [Clearing conditions] * On reset, or in standby mode or module stop mode * When 0 is written to ERS after reading ERS = 1 Error signal indicating detection of parity error has been sent by receiving device [Setting condition] When the error signal is sampled at the low level
1
Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1*7 [Setting condition] When the next serial reception is completed while RDRF = 1*8
Receive Data Register Full*9 0
[Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0
[Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR
1
376
Notes: 1. Can only be written with 0 for flag clearing. 2. Retains its previous state when the RE bit in SCR is cleared to 0 with a multiprocessor format. 3. etu (Elementary Time Unit): Interval for transfer of one bit 4. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 5. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial reception cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission is also disabled. 6. Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. 7. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 8. The receive data prior to the overrun error is retained in RDR, and data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission is also disabled. 9. RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost.
377
RDR0--Receive Data Register 0
Bit : 7 0 R 6 0 R 5 0 R 4 0 R
H'FF7D
3 0 R
SCI0, Smart Card Interface 0
2 0 R 1 0 R 0 0 R
Initial value : Read/Write :
Stores received serial data
SCMR0--Smart Card Mode Register 0
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W
H'FF7E
2 SINV 0 R/W
SCI0, Smart Card Interface 0
1 -- 1 -- 0 SMIF 0 R/W
Smart Card Interface Mode Select 0 1 Smart card interface function is disabled Smart card interface function is enabled
Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form
Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first
378
SMR1--Serial Mode Register 1
Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W
H'FF80
2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
SCI1
Clock Select 0 1 0 1 0 1 o clock o/4 clock o/16 clock o/64 clock
Multiprocessor Mode 0 1 Multiprocessor function disabled Multiprocessor format selected
Stop Bit Length 0 1 Parity Mode 0 1 Even parity*1 Odd parity*2 1 stop bit 2 stop bits
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined. 2. When odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined. Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled*
Notes: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Character Length 0 1 8-bit data 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. With 7-bit data, it is not possible to select LSB-first or MSB-first transfer. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode
379
SMR1--Serial Mode Register 1
Bit : 7 GM Initial value : Read/Write : 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 BCP1 0 R/W
H'FF80
2 BCP0 0 R/W 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 Base Clock Pulse BCP1 BCP0 0 0 1 1 0 1
Smart Card Interface 1
0 CKS0 0 R/W
o clock o/4 clock o/16 clock o/64 clock
Base Clock Pulse 32 clocks 64 clocks 372 clocks 256 clocks
Parity Mode (Set to 1 when using the smart card interface) 0 1 Even parity*1 Odd parity*2
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined. 2. When odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined. Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled*
Notes: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit.
Block Transfer Mode Select 0 1 GSM Mode 0 Normal smart card interface mode operation * TEND flag generated 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit * Clock output on/off control only GSM mode smart card interface mode operation * TEND flag generated 11.0 etu after beginning of start bit * Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control Normal smart card interface mode Block transfer mode
1
Note: etu (Elementary Time Unit): Interval for transfer of one bit
380
BRR1--Bit Rate Register 1
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF81
3 1 R/W
SCI1, Smart Card Interface 1
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Sets the serial transfer bit rate Note: For details, see section 11.2.8, Bit Rate Register (BRR), in the Hardware Manual.
381
SCR1--Serial Control Register 1
Bit :
7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF82
1 CKE1 0 R/W Clock Enable 0 CKE0 0 R/W
SCI1
Initial value : Read/Write :
0
0
Asynchronous mode Synchronous mode
Internal clock/SCK pin functions as I/O port
Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input
1
Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode
1
0
1
Transmit End Interrupt Enable
0 1 Transmit-end interrupt (TEI) request disabled*3
Transmit-end interrupt (TEI) request enabled*3
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received Multiprocessor interrupts enabled*4 Receive-data-full interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled*5 Reception enabled*6
Transmit Enable 0 1 Transmission disabled*7 Transmission enabled*8
Receive Interrupt Enable 0 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled*9 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled Transmit-data-empty interrupt (TXI) request enabled*10
382
Notes: 1. Outputs a clock of the same frequency as the bit rate.
2. Inputs a clock with a frequency 16 times the bit rate.
3. TEI clearing can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. 4. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. 5. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 6. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR setting must be performed to decide the receive format before setting the RE bit to 1. 7. The TDRE flag in SSR is fixed at 1. 8. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transmit format before setting the TE bit to 1. 9. RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. 10. TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0.
383
SCR1--Serial Control Register 1
Bit :
7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W
H'FF82
1 CKE1 0 R/W 0 CKE0 0 R/W
Smart Card Interface 1
Initial value : Read/Write :
Clock Enable (When bit 7 of SMR is set to 1 in smart card interface mode) SCMR SMR SCR setting CKE0 SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SCK pin function
See SCI specification 0 1 0 1 0 1
Operates as port I/O pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin
Transmit End Interrupt Enable 0 1 Transmit-end interrupt (TEI) request disabled*1 Transmit-end interrupt (TEI) request enabled*1
Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When data with MPB = 1 is received Multiprocessor interrupts enabled*2 Receive-data-full interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received
1
Receive Enable 0 1 Reception disabled*3 Reception enabled*4
Transmit Enable 0 1 Transmission disabled*5 Transmission enabled*6
Receive Interrupt Enable 0 1 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled*7 Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled
Transmit Interrupt Enable 0 1 Transmit-data-empty interrupt (TXI) request disabled*8 Transmit-data-empty interrupt (TXI) request enabled
384
Notes: 1. TEI clearing can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0. 2. When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. 3. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 4. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. SMR setting must be performed to decide the receive format before setting the RE bit to 1. 5. The TDRE flag in SSR is fixed at 1. 6. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transmit format before setting the TE bit to 1. 7. RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0. 8. TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0.
TDR1--Transmit Data Register 1
Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W
H'FF83
3 1 R/W
SCI1, Smart Card Interface 1
2 1 R/W 1 1 R/W 0 1 R/W
Initial value : Read/Write :
Stores data for serial transmission
385
SSR1--Serial Status Register 1
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)*1 6 RDRF 0 5 ORER 0 4 FER 0 3 PER 0 2 TEND 1 R
H'FF84
1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1
SCI1
R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1
Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit 0 1 Transmit End 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received*2 [Setting condition] When data with a 1 multiprocessor bit is received
1
Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1*3 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR*4
Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1*5 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, and the stop bit is 0*6
Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1*7 [Setting condition] When the next serial reception is completed while RDRF = 1*8
Receive Data Register Full*9 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR
1
386
Notes: 1. Can only be written with 0 for flag clearing. 2. Retains its previous state when the RE bit in SCR is cleared to 0 with a multiprocessor format. 3. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 4. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial reception cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission is also disabled. 5. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 6. In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial reception cannot be continued while the FER flag is set to 1. In synchronous mode, serial transmission is also disabled. 7. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 8. The receive data prior to the overrun error is retained in RDR, and data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission is also disabled. 9. RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost.
387
SSR1--Serial Status Register 1
Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)*1 6 RDRF 0 5 ORER 0 4 ERS 0 3 PER 0 2 TEND 1 R
H'FF84
1 MPB 0 R 0 MPBT 0 R/W
Smart Card Interface 1
R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1
Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted
Multiprocessor Bit 0 1 Transmit End 0 Transmission in progress [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR Transmission has ended [Setting conditions] * On reset, or in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is 0 * When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu*3 after transmission of a 1-byte serial character when GM = 0 and BLK = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a 1-byte serial character when GM = 0 and BLK = 1 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 and BLK = 1 [Clearing condition] When data with a 0 multiprocessor bit is received*2 [Setting condition] When data with a 1 multiprocessor bit is received
1
Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1*4 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR*5
Error Signal Status*6 0 Data has been received normally, and there is no error signal [Clearing conditions] * On reset, or in standby mode or module stop mode * When 0 is written to ERS after reading ERS =1 Error signal indicating detection of parity error has been sent by receiving device [Setting condition] When the error signal is sampled at the low level
1
Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1*7 [Setting condition] When the next serial reception is completed while RDRF = 1*8
Receive Data Register Full*9 0 [Clearing conditions] * When 0 is written to RDRF after reading RDRF = 1 * When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR
1
Transmit Data Register Empty 0 [Clearing conditions] * When 0 is written to TDRE after reading TDRE = 1 * When the DTC is activated by a TXI interrupt and writes data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR
1
388
Notes: 1. Can only be written with 0 for flag clearing. 2. Retains its previous state when the RE bit in SCR is cleared to 0 with a multiprocessor format. 3. etu (Elementary Time Unit): Interval for transfer of one bit 4. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 5. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Serial reception cannot be continued while the PER flag is set to 1. In synchronous mode, serial transmission is also disabled. 6. Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. 7. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 8. The receive data prior to the overrun error is retained in RDR, and data received subsequently is lost. Serial reception cannot be continued while the ORER flag is set to 1. In synchronous mode, serial transmission is also disabled. 9. RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost.
389
RDR1--Receive Data Register 1
Bit : 7 0 R 6 0 R 5 0 R 4 0 R
H'FF85
3 0 R
SCI1, Smart Card Interface 1
2 0 R 1 0 R 0 0 R
Initial value : Read/Write :
Stores received serial data
SCMR1--Smart Card Mode Register 1
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W
H'FF86
2 SINV 0 R/W
SCI1, Smart Card Interface 1
1 -- 1 -- 0 SMIF 0 R/W
Smart Card Interface Mode Select 0 1 Smart card interface function is disabled Smart card interface function is enabled
Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form
Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first
390
ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL
Bit
-- -- -- -- -- -- -- --
:
A/D Data Register AH A/D Data Register AL A/D Data Register BH A/D Data Register BL A/D Data Register CH A/D Data Register CL A/D Data Register DH A/D Data Register DL
15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R
H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97
7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R
A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter
2 -- 0 R 1 -- 0 R 0 -- 0 R
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value : Read/Write :
Stores the results of A/D conversion Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD
391
ADCSR--A/D Control/Status Register
Bit : 7 ADF Initial value : Read/Write : 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W
H'FF98
3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W
A/D Converter
0 CH0 0 R/W
Channel Select Note: These bits select the analog input channel(s). Ensure that conversion is halted (ADST = 0) before making a channel setting. Group Selection CH2 0 Channel Selection CH1 CH0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Select ADCR Bit 3 Bit 3 CKS1 0 1 CKS 0 1 0 1 Scan Mode 0 1 A/D Start 0 1 A/D conversion stopped * Single mode: A/D conversion is started. Cleared to 0 automatically when conversion ends * Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or transition to standby mode or module stop mode Single mode Scan mode Conversion time = 530 states (max.) Conversion time = 68 states (max.) Conversion time = 266 states (max.) Conversion time = 134 states (max.) (Initial value) Description Single Mode (SCAN = 0) AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Scan Mode (SCAN = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7
Description
A/D Interrupt Enable 0 A/D conversion end interrupt request disabled 1 A/D conversion end interrupt request enabled
A/D End Flag 0 [Clearing conditions] * When 0 is written to the ADF flag after reading ADF = 1 * When the DTC is activated by an ADI interrupt, and ADDR is read [Setting conditions] 1 * Single mode: When A/D conversion ends * Scan mode: When A/D conversion ends on all specified channels Note: * Can only be written with 0 for flag clearing.
392
ADCR--A/D Control Register
Bit : 7 TRGS1 Initial value : Read/Write : 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 --
H'FF99
3 CKS1 1 R/W 2 -- 1 R/W 1 -- 1 --
A/D Converter
0 -- 1 --
Reserved (Only 1 should be written to this bit.) Clock Select Bit 3 CKS1 0 ADCSR Bit 3 CKS 0 1 1 0 1 Timer Trigger Select TRGS1 TRGS1 0 0 1 1 0 1 Description A/D conversion start by external trigger is disabled A/D conversion start by external trigger (TPU) is enabled A/D conversion start by external trigger (8-bit timer) is enabled A/D conversion start by external trigger pin (ADTRG) is enabled Conversion time = 530 states (max.) Conversion time = 68 states (max.) Conversion time = 266 states (max.) Conversion time = 134 states (max.) (Initial value) Description
DADR0--D/A Data Register 0 DADR1--D/A Data Register 1
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFA4 H'FFA5
3 0 R/W 2 0 R/W 1 0
D/A Converter D/A Converter
0 0 R/W
Initial value : Read/Write :
R/W
Stores data for D/A conversion
393
DACR01--D/A Control Register 01
Bit : 7 DAOE1 Initial value : Read/Write : 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 --
H'FFA6
3 -- 1 -- 2 -- 1 -- 1 -- 1 --
D/A Converter
0 -- 1 --
D/A Output Enable 0 0 1 Analog output DA0 is disabled Channel 0 D/A conversion is enabled Analog output DA0 is enabled
D/A Output Enable 1 0 1 Analog output DA1 is disabled Channel 1 D/A conversion is enabled Analog output DA1 is enabled
D/A Conversion Control DAOE1 0 DAOE0 0 1 DAE * 0 Description Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled 1 1 0 0 Channel 0 and 1 D/A conversion enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled 1 1 * Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled * : Don't care
394
PFCR2--Port Function Control Register 2
Bit : 7 -- Initial value : Read/Write : 0 R/W 6 -- 0 R/W 5 1 R/W 4 1 R/W
H'FFAC
3 ASOD 0 R/W 2 -- 0 R 1 -- 0 R 0 -- 0 R
Ports
CS167E CS25E
Reserved Only 0 should be written to these bits
AS Output Disable*1 0 1 PF6 is designated as AS output pin PF6 is designated as I/O port, and does not function as AS output pin
CS25 Enable*1, *2 0 1 CS2, CS3, CS4, and CS5 output disabled (can be used as I/O ports) CS2, CS3, CS4, and CS5 output enabled
CS167 Enable*1, *3 0 1 CS1, CS6, and CS7 output disabled (can be used as I/O ports) CS1, CS6, and CS7 output enabled
Notes: 1. This bit is valid in modes 4 to 6. 2. Clear the DDR bits to 0 before changing the CS25E setting. 3. Clear the DDR bits to 0 before changing the CS167E setting.
395
TCR0--Time Control Register 0 TCR1--Time Control Register 1
Bit :
7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2
H'FFB0 H'FFB1
1 CKS1 0 R/W 0 CKS0 0 R/W
8-Bit Timer Channel 0 8-Bit Timer Channel 1
CKS2 0 R/W
Initial value : Read/Write :
Clock Select 0 0 0 1 1 0 1 1 0 0 Clock input disabled Internal clock: counted at falling edge of o/8 Internal clock: counted at falling edge of o/64 Internal clock: counted at falling edge of o/8192 For channel 0: Count at TCNT1 overflow signal* For channel 1: Count at TCNT0 compare match A* External clock: counted at rising edge External clock: counted at falling edge External clock: counted at both rising and falling edges
1 1 0 1
Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting. Counter Clear 0 0 1 1 0 1 Clear is disabled Clear by compare match A Clear by compare match B Clear by rising edge of external reset input
Timer Overflow Interrupt Enable 0 1 OVF interrupt requests (OVI) are disabled OVF interrupt requests (OVI) are enabled
Compare Match Interrupt Enable A 0 1 CMFA interrupt requests (CMIA) are disabled CMFA interrupt requests (CMIA) are enabled
Compare Match Interrupt Enable B 0 1 CMFB interrupt requests (CMIB) are disabled CMFB interrupt requests (CMIB) are enabled
396
TCSR0--Timer Control/Status Register 0 TCSR1--Timer Control/Status Register 1
TCSR0 Bit :
7 CMFB 0 R/(W)* 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 5 OVF 0 R/(W)* 4
H'FFB2 H'FFB3
3 OS3 0 R/W 3 OS3 0 R/W 2 OS2 0 R/W 2 OS2 0 R/W
8-Bit Timer Channel 0 8-Bit Timer Channel 1
1 OS1 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W 0 OS0 0 R/W
ADTE 0 R/W 4 -- 1 --
Initial value : Read/Write : TCSR1 Bit :
Initial value : Read/Write :
Output Select 0 0 1 1 0 1 No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs Output is inverted when compare match A occurs (toggle output)
Output Select 0 0 1 1 0 1 No change when compare match B occurs 0 is output when compare match B occurs 1 is output when compare match B occurs Output is inverted when compare match B occurs (toggle output)
A/D Trigger Enable (TCSR0 only) 0 1 A/D converter start requests by compare match A are disabled A/D converter start requests by compare match A are enabled
Timer Overflow Flag 0 1 [Clearing condition] When 0 is written to OVF after reading OVF = 1 [Setting condition] When TCNT overflows (changes from H'FF to H'00)
Compare Match Flag A 0 [Clearing conditions] * When 0 is written to CMFA after reading CMFA = 1 * When the DTC is activated by a CMIA interrupt, while the DISEL bit of MRB in DTC is 0 [Setting condition] When TCNT matches TCORA
1
Compare Match Flag B 0 [Clearing conditions] * When 0 is written to CMFB after reading CMFB = 1 * When the DTC is activated by a CMIB interrupt, while the DISEL bit of MRB in DTC is 0 [Setting condition] When TCNT matches TCORB
1
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
397
TCORA0--Time Constant Register A0 TCORA1--Time Constant Register A1
TCORA0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFB4 H'FFB5
8-Bit Timer Channel 0 8-Bit Timer Channel 1
TCORA1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0--Time Constant Register B0 TCORB1--Time Constant Register B1
TCORB0 Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFB6 H'FFB7
8-Bit Timer Channel 0 8-Bit Timer Channel 1
TCORB1
7 1
6 1
5 1
4 1
3 1
2 1
1 1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNT0--Timer Counter 0 TCNT1--Timer Counter 1
TCNT0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FFB8 H'FFB9
8-Bit Timer Channel 0 8-Bit Timer Channel 1
TCNT1
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
398
TCSR--Timer Control/Status Register
Bit : 7 OVF Initial value : Read/Write : 0 R/(W)*1 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 --
H'FFBC (W) H'FFBC (R)
3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0
WDT
CKS0 0 R/W
Clock Select CKS2 CKS1 CKS0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Clock Overflow period* (when o = 20 MHz) 819.2s 1.6ms 6.6ms 26.2ms 104.9ms 419.4ms 1.68s
o/2 (Initial value) 25.6s o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. Timer Enable 0 1 TCNT is initialized to H'00 and halted TCNT counts
Timer Mode Select 0 1 Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer mode: Generates the WDTOVF signal*2 when TCNT overflows
Overflow Flag 0 1 [Clearing condition] When 0 is written to OVF after reading OVF = 1 [Setting condition] When TCNT overflows from H'FF to H'00 in interval timer mode
Notes: The method for writing to TCSR is different from that for general registers to prevent accidental overwriting. For details, see section 10.2.4, Notes on Register Access, in the Hardware Manual. 1. Can only be written with 0 for flag clearing. 2. The WDTOVF pin function cannot be used in the F-ZTAT version.
399
TCNT--Timer Counter
Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W
H'FFBC (W) H'FFBD (R)
3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
WDT
Initial value : Read/Write : Note:
The method for writing to TCNT different from that for general registers to prevent accidental overwritting. For details, see section 10.2.4, Notes on Register Access, in the Hardware Manual.
RSTCSR--Reset Control/Status Register
Bit : 7 WOVF Initial value : Read/Write : 0 R/(W)* 6 RSTE 0 R/W 5 -- 0 R/W 4 -- 1 --
H'FFBE (W) H'FFBF (R)
3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 --
WDT
Reserved This bit cannot be modified Reset Enable 0 1 Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows
Note: * The modules in the chip are not reset, but TCNT and TCSR in WDT are reset. Watchdog Timer Overflow Flag 0 1 [Clearing condition] When 0 is written to WOVF after reading WOVF = 1 [Setting condition] When TCNT overflows (changes from H'FF to H'00) during watchdog timer operation
Notes: The method for writing to RSTCSR is different from that for general registers to prevent accidental overwriting. For details, see section 10.2.4, Notes on Register Access, in the Hardware Manual. * Can only be written with 0 for flag clearing.
400
TSTR--Timer Start Register
Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 CST5 0 R/W 4 CST4 0 R/W
H'FFC0
3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W
TPU
Counter Start 0 1 TCNTn count operation is stopped TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value.
TSYR--Timer Synchro Register
Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 SYNC5 0 R/W 4 SYNC4 0 R/W
H'FFC1
3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W
TPU
Timer Synchronization 0 1 TCNTn operates independently (TCNT presetting/ clearing is unrelated to other channels) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 5 to 0) Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR.
401
FLMCR1--Flash Memory Control Register 1 H'FFC8 Flash Memory (Valid in H8S/2318 F-ZTAT and H8S/2315 F-ZTAT versions only)
Bit : 7 FWE Initial value : Read/Write : 1/0
*1
6 SWE 0 R/W
5 ESU 0 R/W
4 PSU 0 R/W
3 EV 0 R/W
2 PV 0 R/W
1 E 0 R/W
0 P 0 R/W
R
Program*2 0 1 Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1
Erase*2 0 1 Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1
Program-Verify*2 0 1 Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1
Erase-Verify*2 0 1 Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1
Program Setup*2 0 1 Program setup cleared Program setup [Setting condition] When FWE = 1 and SWE = 1
Software Write Enable*2 0 1 Writes disabled Writes enabled [Setting condition] When FWE = 1
Erase Setup*2 0 1 Erase setup cleared Erase setup [Setting condition] When FWE = 1 and SWE = 1
Flash Write Enable 0 1 When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin
Notes: 1. Determined by the state of the FWE pin. 2. Valid for addresses H'000000 to H'03FFFF in H8S/2318 F-ZTAT and H'000000 to H'05FFFF in H8S/2315 F-ZTAT.
402
FLMCR1--Flash Memory Control Register 1
H'FFC8 Flash Memory (Valid in H8S/2319 F-ZTAT version only)
4 3 EV1 0 R/W 2 PV1 0 R/W 1 E1 0 R/W 0 P1 0 R/W
Bit
:
7 FWE 1 R
6 SWE1 0 R/W
5 ESU1 0 R/W
PSU1 0 R/W
Initial value : Read/Write :
Program 1* 0 1 Program mode cleared Transition to program mode [Setting condition] When SWE1 = 1 and PSU1 = 1
Erase 1* 0 1 Erase mode cleared Transition to erase mode [Setting condition] When SWE1 = 1 and ESU1 = 1
Program-Verify 1* 0 1 Program-verify mode cleared Transition to program-verify mode [Setting condition] When SWE1 = 1
Erase-Verify 1* 0 1 Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When SWE1 = 1
Program Setup 1* 0 1 Program setup cleared Program setup [Setting condition] When SWE1 = 1
Software Write Enable 1* 0 1 Writes disabled Writes enabled
Erase Setup 1* 0 1 Erase setup cleared Erase setup [Setting condition] When SWE1 = 1
Flash Write Enable Always read as 1 and cannot be written to.
Note: * Valid for addresses H'000000 to H'03FFFF.
403
FLMCR2--Flash Memory Control Register 2 H'FFC9 Flash Memory (Valid in H8S/2318 F-ZTAT and H8S/2315 F-ZTAT versions only)
Bit : 7 FLER Initial value : Read/Write : 0 R 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 --
Flash Memory Error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 17.8.3, Error Protection, in the Hardware Manual.
1
404
FLMCR2--Flash Memory Control Register 2
Bit : 7 FLER Initial value : Read/Write : 0 R 6 SWE2 0 R/W 5 ESU2 0 R/W 4
H'FFC9 Flash Memory (Valid in H8S/2319 F-ZTAT version only)
3 EV2 0 R/W 2 PV2 0 R/W 1 E2 0 R/W 0 P2 0 R/W
PSU2 0 R/W
Program 2* 0 1 Program mode cleared Transition to program mode [Setting condition] When SWE2 = 1 and PSU2 = 1
Erase 2* 0 1 Erase mode cleared Transition to erase mode [Setting condition] When SWE2 = 1 and ESU2 = 1
Program-Verify 2* 0 1 Program-verify mode cleared Transition to program-verify mode [Setting condition] When SWE2 = 1
Erase-Verify 2* 0 1 Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When SWE2 = 1
Program Setup 2* 0 1 Program setup cleared Program setup [Setting condition] When SWE2 = 1
Software Write Enable 2* 0 1 Writes disabled Writes enabled
Erase Setup 2* 0 1 Erase setup cleared Erase setup [Setting condition] When SWE2 = 1
Flash Memory Error 0
Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 17.8.3, Error Protection, in the Hardware Manual.
1
Note: * Valid for addresses H'040000 to H'07FFFF. 405
EBR1--Erase Block Register 1 EBR2--Erase Block Register 2
H'FFCA H'FFCB
Flash Memory Flash Memory (Valid only in F-ZTAT version)
2 EB2 0 R/W 2 EB10 0 R/W 1 EB1 0 R/W 1 EB9 0 R/W 0 EB0 0 R/W 0 EB8 0 R/W
Bit EBR1
:
7 EB7 0 R/W 7 EB15*2 0 R/W*2
6 EB6 0 R/W 6 EB14*2 0 R/W*2
5 EB5 0 R/W 5 EB13*1 0 R/W*1
4 EB4 0 R/W 4 EB12*1 0 R/W*1
3 EB3 0 R/W 3 EB11 0 R/W
Initial value : Read/Write : Bit EBR2 Initial value : Read/Write : :
Notes: 1. Valid in H8S/2319 F-ZTAT and H8S/2315 F-ZTAT versions. 2. Valid in H8S/2319 F-ZTAT version.
406
TCR0--Timer Control Register 0
Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W
H'FFD0
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
TPU0
CKEG1 CKEG0
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input
Note: The internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if o/1 or overflow/underflow on another channel is selected as the input clock.
Counter Clear 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture*2 TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
407
TMDR0--Timer Mode Register 0
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W
H'FFD1
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU0
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
* : Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.
TGRA Buffer Operation 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation
TGRB Buffer Operation 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation
408
TIOR0H--Timer I/O Control Register 0H
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W
H'FFD2
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU0
TGR0A I/O Control 0 0 0 0 TGR0A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0A is input 1 capture * register * Capture input source is TIOCA0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock * : Don't care TGR0B Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0B is input capture register Capture input source is TIOCB0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock * : Don't care Note: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture does not occur.
0 output at compare match 1 output at compare match Toggle output at compare match
1
1 1 TGR0B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * *
409
TIOR0L--Timer I/O Control Register 0L
Bit : : Initial value : Read/Write : 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W
H'FFD3
1 IOC1 0 R/W 0 IOC0 0 R/W
TPU0
TGR0C I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0C Capture input is input source is capture TIOCC0 pin register* Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0C Output disabled is output compare Initial output is register* 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock
* : Don't care Note: When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare does not occur.
TGR0D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0D is input capture register
*2
TGR0D Output disabled is output compare Initial output is register 0 output
*2
0 output at compare match 1 output at compare match Toggle output at compare match
Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input source is TIOCD0 pin Capture input source is channel 1/count clock Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 count-up/ count-down*1
* : Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture does not occur. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare does not occur. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.
410
TIER0--Timer Interrupt Enable Register 0
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3
H'FFD4
2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W
TPU0
TGIED 0 R/W
TGR Interrupt Enable A 0 1 Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled
TGR Interrupt Enable C 0 1 Interrupt request (TGIC) by TGFC bit disabled Interrupt request (TGIC) by TGFC bit enabled
TGR Interrupt Enable D 0 1 Interrupt request (TGID) by TGFD bit disabled Interrupt request (TGID) by TGFD bit enabled
Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
411
TSR0--Timer Status Register 0
Bit :
7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)*
H'FFD5
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU0
Initial value : Read/Write :
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Input Capture/Output Compare Flag C 0 [Clearing conditions] * When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register
1
Input Capture/Output Compare Flag D 0 [Clearing conditions] * When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register
1
Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
412
TCNT0--Timer Counter 0
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FFD6
7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU0
0 0
Initial value : Read/Write :
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
TGR0A--Timer General Register 0A TGR0B--Timer General Register 0B TGR0C--Timer General Register 0C TGR0D--Timer General Register 0D
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFD8 H'FFDA H'FFDC H'FFDE
7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU0 TPU0 TPU0 TPU0
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
413
TCR1--Timer Control Register 1
Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W
H'FFE0
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
TPU1
CKEG1 CKEG0
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on o/256 Counts on TCNT2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase counting mode.
Clock Edge* 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges
Note: This setting is ignored when channel 1 is in phase counting mode. The internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if o/1 or overflow/underflow on another channel is selected as the input clock.
Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
414
TMDR1--Timer Mode Register 1
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 --
H'FFE1
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU1
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
* : Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0.
415
TIOR1--Timer I/O Control Register 1
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2
H'FFE2
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU1
IOA2 0 R/W
TGR1A I/O Control
0 0 0
0 1
1
0 1
TGR1A Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
1
0
0 1
Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR1A is input capture register Capture input source is TIOCA1 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0A channel 0/TGR0A compare match/ compare match/ input capture input capture * : Don't care
1
0 1
1
0
0
0 1
1 1 *
* *
TGR1B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1B is input capture register Capture input source is TIOCB1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0C TGR0C compare match/input compare match/ capture input capture * : Don't care TGR1B Output disabled is output compare Initial output is register 0 output
0 output at compare match 1 output at compare match Toggle output at compare match
416
TIER1--Timer Interrupt Enable Register 1
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 --
H'FFE4
2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A
TPU1
0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt request (TCIU) by TCFU disabled Interrupt request (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
417
TSR1--Timer Status Register 1
Bit :
7 TCFD 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 --
H'FFE5
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU1
Initial value : Read/Write :
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
418
TCNT1--Timer Counter 1
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FFE6
7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU1
0 0
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR1A--Timer General Register 1A TGR1B--Timer General Register 1B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1
H'FFE8 H'FFEA
8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU1 TPU1
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
419
TCR2--Timer Control Register 2
Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0
H'FFF0
2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
TPU2
CKEG1 CKEG0 R/W
Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on o/1024
Note: This setting is ignored when channel 2 is in phase counting mode. Clock Edge* 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges
Note: This setting is ignored when channel 2 is in phase counting mode. The internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if o/1 or overflow/underflow on another channel is selected as the input clock. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*
Note: * Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
420
TMDR2--Timer Mode Register 2
Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 --
H'FFF1
3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
TPU2
Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 --
* : Don't care Note: MD3 is a reserved bit. In a write, it should always be written with 0.
421
TIOR2--Timer I/O Control Register 2
Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W
H'FFF2
1 IOA1 0 R/W 0 IOA0 0 R/W
TPU2
TGR2A I/O Control 0 0 0 0 TGR2A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR2A is input 1 capture * register Capture input source is TIOCA2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges
* : Don't care
Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match
1
1
TGR2B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR2B is input capture register Capture input source is TIOCB2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges
* : Don't care
TGR2B is output compare register
Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match
422
TIER2--Timer Interrupt Enable Register 2
Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 --
H'FFF4
2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1
TPU2
Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled
TGR Interrupt Enable B 0 1 Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by TGFB bit enabled
Overflow Interrupt Enable 0 1 Interrupt request (TCIV) by TCFV disabled Interrupt request (TCIV) by TCFV enabled
Underflow Interrupt Enable 0 1 Interrupt request (TCIU) by TCFU disabled Interrupt request (TCIU) by TCFU enabled
A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled
423
TSR2--Timer Status Register 2
Bit :
7 TCFD 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 --
H'FFF5
1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
TPU2
Initial value : Read/Write :
Input Capture/Output Compare Flag A 0 [Clearing conditions] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register
1
Input Capture/Output Compare Flag B 0 [Clearing conditions] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register
1
Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 )
Note: * Can only be written with 0 for flag clearing.
424
TCNT2--Timer Counter 2
Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0
H'FFF6
7 0 6 0 5 0 4 0 3 0 2 0 1 0
TPU2
0 0
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
TGR2A--Timer General Register 2A TGR2B--Timer General Register 2B
Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1
H'FFF8 H'FFFA
7 1 6 1 5 1 4 1 3 1 2 1 1 1
TPU2 TPU2
0 1
Initial value :
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
425
426
H8S/2319, H8S/2318 Series, H8S/2319 F-ZTATTM, H8S/2318 F-ZTATTM, H8S/2315 F-ZTATTM Reference Manual
Publication Date: 1st Edition, November 1999 2nd Edition, August 2000 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

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